More divider cleanup

wally-pipelined/src/generic/adder.sv

@@ -0,0 +1,35 @@
+///////////////////////////////////////////
+// adder.sv
+//
+// Written: David_Harris@hmc.edu 2 October 2021
+// Modified: 
+//
+// Purpose: Adder
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module adder #(parameter WIDTH=8) (
+  input  logic [WIDTH-1:0] a, b,
+  output logic [WIDTH-1:0] y);
+
+  assign y = a + b;
+endmodule 
+
+

wally-pipelined/src/muldiv/div.sv

@@ -278,13 +278,14 @@ module otf #(parameter WIDTH=8)
    assign QMstar = R1Q;
 
 endmodule // otf8
-
+/*
 module adder #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b,
 				   output logic [WIDTH-1:0] y);
 
    assign y = a + b;
 
 endmodule // adder
+*/
 
 module fa (input logic a, b, c, output logic sum, carry);
 

wally-pipelined/src/muldiv/intdivrestoring.sv

@@ -61,15 +61,12 @@ module intdivrestoring (
   flopenrc #(1) SignXMReg(clk, reset, FlushM, ~StallM, SignXE, SignXM);
   flopenrc #(`XLEN) XSavedMReg(clk, reset, FlushM, ~StallM, XSavedE, XSavedM); // is this truly necessary?
 
-  // Take absolute value for signed operations
+  // Take absolute value for signed operations, and negate D to handle subtraction in divider stages
   neg #(`XLEN) negd(DSavedE, DnE);
   mux2 #(`XLEN) dabsmux(DnE, DSavedE, SignedDivideE & SignDE, DAbsB);  // take absolute value for signed operations, and negate for subtraction setp
   neg #(`XLEN) negx(XSavedE, XnE);
   mux2 #(`XLEN) xabsmux(XSavedE, XnE, SignedDivideE & SignXE, Xinit);  // need original X as remainder if doing divide by 0
 
-  // Negate D for subtraction
-  //assign DAbsB = ~Din;
-  // *** merge this into dabsmux if possible
    // Put suffixes on Xinit, init->DivInitE, Wn, XQn
 
   // initialization multiplexers on first cycle of operation (one cycle after start is asserted)

wally-pipelined/src/muldiv/intdivrestoringstep.sv

@@ -33,7 +33,8 @@ module intdivrestoringstep(
   logic qi, qib;
   
   assign {WShift, XQOut} = {W[`XLEN-2:0], XQ, qi};
-  assign {qib, WPrime} = {1'b0, WShift} + {1'b1, DAbsB} /*+ 1*/; // subtractor, carry out determines quotient bit ***replace with add
+  adder #(`XLEN+1) wdsub({1'b0, WShift}, {1'b1, DAbsB}, {qib, WPrime});
+  //assign {qib, WPrime} = {1'b0, WShift} + {1'b1, DAbsB}; // effective subtractor, carry out determines quotient bit
   assign qi = ~qib;
   mux2 #(`XLEN) wrestoremux(WShift, WPrime, qi, WOut);
 endmodule