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finishing merge conflict changes

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This commit is contained in:
Shriya Nadgauda 2021-05-03 22:15:05 -04:00
parent 52e0b703b7
commit 0be6b81df9
3 changed files with 0 additions and 15 deletions
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5
wally-pipelined/config/rv32ic/wally-config.vh
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@ -68,13 +68,8 @@
`define BOOTTIMBASE 32'h00000000 `define BOOTTIMBASE 32'h00000000
`define BOOTTIMRANGE 32'h00003FFF `define BOOTTIMRANGE 32'h00003FFF
<<<<<<< HEAD
`define TIMBASE 32'h80000000
`define TIMRANGE 32'h0FFFFFFF
=======
`define TIMBASE 32'h80000000 `define TIMBASE 32'h80000000
`define TIMRANGE 32'h07FFFFFF `define TIMRANGE 32'h07FFFFFF
>>>>>>> 8ba2d3f3f5386454804de1a4036360b1c2c32bc0
`define CLINTBASE 32'h02000000 `define CLINTBASE 32'h02000000
`define CLINTRANGE 32'h0000FFFF `define CLINTRANGE 32'h0000FFFF
`define GPIOBASE 32'h10012000 `define GPIOBASE 32'h10012000

5
wally-pipelined/config/rv64ic/wally-config.vh
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@ -72,13 +72,8 @@
`define BOOTTIMBASE 32'h00000000 `define BOOTTIMBASE 32'h00000000
`define BOOTTIMRANGE 32'h00003FFF `define BOOTTIMRANGE 32'h00003FFF
<<<<<<< HEAD
`define TIMBASE 32'h80000000
`define TIMRANGE 32'h0FFFFFFF
=======
`define TIMBASE 32'h80000000 `define TIMBASE 32'h80000000
`define TIMRANGE 32'h07FFFFFF `define TIMRANGE 32'h07FFFFFF
>>>>>>> 8ba2d3f3f5386454804de1a4036360b1c2c32bc0
`define CLINTBASE 32'h02000000 `define CLINTBASE 32'h02000000
`define CLINTRANGE 32'h0000FFFF `define CLINTRANGE 32'h0000FFFF
`define GPIOBASE 32'h10012000 `define GPIOBASE 32'h10012000

5
wally-pipelined/testbench/testbench-imperas.sv
View File

@ -38,13 +38,8 @@ module testbench();
parameter SIGNATURESIZE = 5000000; parameter SIGNATURESIZE = 5000000;
int test, i, errors, totalerrors; int test, i, errors, totalerrors;
<<<<<<< HEAD
logic [31:0] sig32[0:SIGNATURESIZE];
logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
=======
logic [31:0] sig32[0:MAXSIGLEN]; logic [31:0] sig32[0:MAXSIGLEN];
logic [`XLEN-1:0] signature[0:MAXSIGLEN]; logic [`XLEN-1:0] signature[0:MAXSIGLEN];
>>>>>>> 8ba2d3f3f5386454804de1a4036360b1c2c32bc0
logic [`XLEN-1:0] testadr; logic [`XLEN-1:0] testadr;
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
logic [31:0] InstrW; logic [31:0] InstrW;