From 0bc3bcf406cffd338c5d6a24baadc38c451afe30 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Dec 2021 23:27:37 -0600
Subject: [PATCH] Fixed bug on icache spill.  if the cpu stalled on the
 completion it was possible to use the wrong address for the sram read.  Also
 miss spill hit always selected the wrong address.

---
 wally-pipelined/src/cache/icachefsm.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index dd4e2e4ad..aa49a55e8 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -294,8 +294,8 @@ module icachefsm
           ICacheStallF = 1'b0;
 		  LRUWriteEn = 1'b1;
 		  if(StallF) begin
-			NextState = STATE_CPU_BUSY;
-			SelAdr = 2'b01;
+			NextState = STATE_CPU_BUSY_SPILL;
+			SelAdr = 2'b10;
 		  end else begin
             NextState = STATE_READY;
 		  end