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https://github.com/openhwgroup/cvw
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fix missing input/output on debug module for lsu
This commit is contained in:
James Stine
parent
f5e01bea20
commit
0bb6a8866a
111
src/lsu/lsu.sv
111
src/lsu/lsu.sv
@ -33,67 +33,72 @@
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module lsu import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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output logic LSUStallM, // LSU stalls pipeline during a multicycle operation
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output logic LSUStallM, // LSU stalls pipeline during a multicycle operation
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// connected to cpu (controls)
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input logic [1:0] MemRWE, // Read/Write control
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input logic [1:0] MemRWM, // Read/Write control
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input logic [2:0] Funct3M, // Size of memory operation
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input logic [6:0] Funct7M, // Atomic memory operation function
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input logic [1:0] AtomicM, // Atomic memory operation
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input logic FlushDCacheM, // Flush D cache to next level of memory
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input logic [3:0] CMOpM, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
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input logic LSUPrefetchM, // Prefetch; presently unused
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output logic CommittedM, // Delay interrupts while memory operation in flight
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output logic SquashSCW, // Store conditional failed disable write to GPR
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output logic DCacheMiss, // D cache miss for performance counters
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output logic DCacheAccess, // D cache memory access for performance counters
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input logic [1:0] MemRWE, // Read/Write control
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input logic [1:0] MemRWM, // Read/Write control
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input logic [2:0] Funct3M, // Size of memory operation
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input logic [6:0] Funct7M, // Atomic memory operation function
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input logic [1:0] AtomicM, // Atomic memory operation
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input logic FlushDCacheM, // Flush D cache to next level of memory
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input logic [3:0] CMOpM, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
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input logic LSUPrefetchM, // Prefetch; presently unused
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output logic CommittedM, // Delay interrupts while memory operation in flight
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output logic SquashSCW, // Store conditional failed disable write to GPR
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output logic DCacheMiss, // D cache miss for performance counters
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output logic DCacheAccess, // D cache memory access for performance counters
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// address and write data
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input logic [P.XLEN-1:0] IEUAdrE, // Execution stage memory address
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output logic [P.XLEN-1:0] IEUAdrM, // Memory stage memory address
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input logic [P.XLEN-1:0] WriteDataM, // Write data from IEU
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output logic [P.LLEN-1:0] ReadDataW, // Read data to IEU or FPU
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input logic [P.XLEN-1:0] IEUAdrE, // Execution stage memory address
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output logic [P.XLEN-1:0] IEUAdrM, // Memory stage memory address
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input logic [P.XLEN-1:0] WriteDataM, // Write data from IEU
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output logic [P.LLEN-1:0] ReadDataW, // Read data to IEU or FPU
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// cpu privilege
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input logic [1:0] PrivilegeModeW, // Current privilege mode
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input logic BigEndianM, // Swap byte order to big endian
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input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
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output logic DCacheStallM, // D$ busy with multicycle operation
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input logic [1:0] PrivilegeModeW, // Current privilege mode
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input logic BigEndianM, // Swap byte order to big endian
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input logic sfencevmaM, // Virtual memory address fence, invalidate TLB entries
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output logic DCacheStallM, // D$ busy with multicycle operation
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// fpu
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input logic [P.FLEN-1:0] FWriteDataM, // Write data from FPU
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input logic FpLoadStoreM, // Selects FPU as store for write data
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input logic [P.FLEN-1:0] FWriteDataM, // Write data from FPU
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input logic FpLoadStoreM, // Selects FPU as store for write data
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// faults
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output logic LoadPageFaultM, StoreAmoPageFaultM, // Page fault exceptions
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output logic LoadMisalignedFaultM, // Load address misaligned fault
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output logic LoadAccessFaultM, // Load access fault (PMA)
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output logic HPTWInstrAccessFaultF, // HPTW generated access fault during instruction fetch
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output logic HPTWInstrPageFaultF, // HPTW generated access fault during instruction fetch
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output logic LoadPageFaultM, StoreAmoPageFaultM, // Page fault exceptions
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output logic LoadMisalignedFaultM, // Load address misaligned fault
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output logic LoadAccessFaultM, // Load access fault (PMA)
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output logic HPTWInstrAccessFaultF, // HPTW generated access fault during instruction fetch
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output logic HPTWInstrPageFaultF, // HPTW generated access fault during instruction fetch
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// cpu hazard unit (trap)
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output logic StoreAmoMisalignedFaultM, // Store or AMO address misaligned fault
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output logic StoreAmoAccessFaultM, // Store or AMO access fault
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output logic StoreAmoMisalignedFaultM, // Store or AMO address misaligned fault
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output logic StoreAmoAccessFaultM, // Store or AMO access fault
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// connect to ahb
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output logic [P.PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU
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input logic [P.XLEN-1:0] HRDATA, // Bus read data from LSU to EBU
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output logic [P.XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU
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input logic LSUHREADY, // Bus ready from LSU to EBU
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output logic LSUHWRITE, // Bus write operation from LSU to EBU
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output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU
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output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU
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output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU
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output logic [P.XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU
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output logic [P.PA_BITS-1:0] LSUHADDR, // Bus address from LSU to EBU
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input logic [P.XLEN-1:0] HRDATA, // Bus read data from LSU to EBU
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output logic [P.XLEN-1:0] LSUHWDATA, // Bus write data from LSU to EBU
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input logic LSUHREADY, // Bus ready from LSU to EBU
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output logic LSUHWRITE, // Bus write operation from LSU to EBU
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output logic [2:0] LSUHSIZE, // Bus operation size from LSU to EBU
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output logic [2:0] LSUHBURST, // Bus burst from LSU to EBU
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output logic [1:0] LSUHTRANS, // Bus transaction type from LSU to EBU
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output logic [P.XLEN/8-1:0] LSUHWSTRB, // Bus byte write enables from LSU to EBU
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// page table walker
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input logic [P.XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
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input logic [1:0] STATUS_MPP, // Machine previous privilege mode
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input logic ENVCFG_PBMTE, // Page-based memory types enabled
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input logic ENVCFG_ADUE, // HPTW A/D Update enable
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input logic [P.XLEN-1:0] PCSpillF, // Fetch PC
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input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
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input logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits
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output logic [P.XLEN-1:0] PTE, // Page table entry write to ITLB
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output logic [1:0] PageType, // Type of page table entry to write to ITLB
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output logic ITLBWriteF, // Write PTE to ITLB
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output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE
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input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
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input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0] // PMP address from privileged unit
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input logic [P.XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
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input logic [1:0] STATUS_MPP, // Machine previous privilege mode
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input logic ENVCFG_PBMTE, // Page-based memory types enabled
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input logic ENVCFG_ADUE, // HPTW A/D Update enable
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input logic [P.XLEN-1:0] PCSpillF, // Fetch PC
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input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
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input logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits
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output logic [P.XLEN-1:0] PTE, // Page table entry write to ITLB
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output logic [1:0] PageType, // Type of page table entry to write to ITLB
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output logic ITLBWriteF, // Write PTE to ITLB
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output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE
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input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration from privileged unit
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input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP address from privileged unit
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// Debug scan chain
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input logic DebugCapture,
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input logic DebugScanEn,
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input logic DebugScanIn,
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output logic DebugScanOut
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);
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localparam logic MISALIGN_SUPPORT = P.ZICCLSM_SUPPORTED & P.DCACHE_SUPPORTED;
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localparam MLEN = MISALIGN_SUPPORT ? 2*P.LLEN : P.LLEN; // widen buffer for misaligned accessess
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