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Fixed path to riscvOVPsimPlus

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This commit is contained in:
David Harris 2022-01-21 00:12:14 +00:00
parent d1162eeebf
commit 0bb63e9ad1
4 changed files with 7 additions and 43 deletions
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4
Makefile
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@ -9,7 +9,9 @@ install:
cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/ cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
# tests/linux-testgen/linux-testvectors/tvLinker.sh # needs to be run in local directory cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory
rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
regression: regression:
make -C pipelined/regression make -C pipelined/regression

38
examples/asm/sumtest/fir.c
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@ -1,38 +0,0 @@
// fir.C
// David_Harris@hmc.edu 25 December 2021
// Finite Impulse Response Filter
#include <math.h>
#define N 2000
#define M 100
#define PI 3.14159
double fir(double a[], double c[], double y[], int N, int M) {
int i, j
for (i=0; i<N-M; i++) {
y[i] = 0;
for (j=0; j<M; j++) {
y[i] += c[j] * a[M+i-j];
}
}
}
int main(void) {
double a[N], c[M], y[N-M];
int i;
// // step input with overlying high frequency sinusoid
for (i=0; i<N; i++) a[i] = (i < N/2) + 0.5 * cos(2*PI*i/50);
// filter coeffieints: replace with a sinc function with sharper response
//for (i=0; i<M; i++) c[i] = 1.0/M; // low pass filter with equal coefficients
for (i=0; i<M; i++) c[i] = 2.0*B*(sin(2.0*B*i/10)/(2.0*B*i/10)); // low pass filter with equal coefficients
// inline assembly to measure time, with macro
fir(a, c, y, N, M);
// measure time again
// *** generate signature
// *** write_tohost
}

4
examples/verilog/riscvsingle/riscvsingle.sv
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@ -117,7 +117,7 @@ module testbench();
logic MemWrite; logic MemWrite;
// instantiate device to be tested // instantiate device to be tested
riscvsinglehart dut(clk, reset, WriteData, IEUAdr, MemWrite); riscvsinglecore dut(clk, reset, WriteData, IEUAdr, MemWrite);
// initialize test // initialize test
initial begin initial begin
@ -143,7 +143,7 @@ module testbench();
end end
endmodule endmodule
module riscvsinglehart( module riscvsinglecore(
input logic clk, reset, input logic clk, reset,
output logic [31:0] WriteData, IEUAdr, output logic [31:0] WriteData, IEUAdr,
output logic MemWrite); output logic MemWrite);

4
pipelined/regression/Makefile
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@ -11,8 +11,8 @@ make all:
# *** Build old tests/imperas-riscv-tests for now; # *** Build old tests/imperas-riscv-tests for now;
# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
# Also delete bin/exe2memfile at that point # Also delete bin/exe2memfile at that point
# make -C ../../tests/imperas-riscv-tests make -C ../../tests/imperas-riscv-tests
# make -C ../../tests/imperas-riscv-tests XLEN=64 make -C ../../tests/imperas-riscv-tests XLEN=64
cd ../../tests/imperas-riscv-tests; exe2memfile.pl work/*/*.elf cd ../../tests/imperas-riscv-tests; exe2memfile.pl work/*/*.elf