mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Improved RAS again.
This commit is contained in:
Ross Thompson
parent
172c40d44b
commit
0b9f787635
@ -41,12 +41,12 @@ add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpi
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -expand -group PCS /testbench/dut/core/PCF
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add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD
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add wave -noupdate -expand -group PCS /testbench/dut/core/PCE
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add wave -noupdate -expand -group PCS /testbench/dut/core/PCM
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add wave -noupdate -expand -group PCS /testbench/PCW
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add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group PCS /testbench/dut/core/PCF
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add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
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add wave -noupdate -group PCS /testbench/dut/core/PCE
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add wave -noupdate -group PCS /testbench/dut/core/PCM
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add wave -noupdate -group PCS /testbench/PCW
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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@ -55,15 +55,15 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM
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add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM
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add wave -noupdate -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
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@ -85,25 +85,18 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
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add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC
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add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
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add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
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add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
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add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
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add wave -noupdate -group Bpred -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
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@ -148,20 +141,15 @@ add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
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add wave -noupdate -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUReq
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUReq
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount
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add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/FinalBeat
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold
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add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
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add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
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add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
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@ -463,10 +451,6 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/P
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add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
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add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
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add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
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add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
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add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
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add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
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add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
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add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF
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add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
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add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
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@ -484,7 +468,6 @@ add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
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add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss
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add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
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add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
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add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
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add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
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add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
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add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
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@ -571,7 +554,6 @@ add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E
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add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE
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add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE
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add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E
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add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/MDUE
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add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E
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add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X
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add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y
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@ -603,8 +585,15 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/Br
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/ra1
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/memory/rd1
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCE
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/IEUAdrE
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {116741 ns} 0}
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WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {125611 ns} 0}
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quietly wave cursor active 5
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 194
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@ -620,4 +609,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {118528 ns} {128752 ns}
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WaveRestoreZoom {79760 ns} {171462 ns}
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@ -32,15 +32,13 @@ module RASPredictor
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#(parameter int StackSize = 16
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)
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(input logic clk,
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input logic reset, StallF, StallD, StallE,
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input logic reset, StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
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output logic [`XLEN-1:0] RASPCF,
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input logic [3:0] WrongPredInstrClassD,
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input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF,
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input logic [`XLEN-1:0] PCLinkE
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);
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// *** need to update so it either doesn't push until the memory stage
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// or need to repair flushed push.
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// *** need to repair popped and then flushed returns.
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logic CounterEn;
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localparam Depth = $clog2(StackSize);
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@ -50,19 +48,20 @@ module RASPredictor
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integer index;
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logic PopF;
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logic PushE;
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logic RepairD;
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assign PopF = PredInstrClassF[2] & ~StallF;
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assign PushE = InstrClassE[3] & ~StallE;
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assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
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assign RepairD = InstrClassD[2] & ~StallE & ~FlushE;
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assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
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assign CounterEn = PopF | PushE | WrongPredInstrClassD[2];
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assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1;
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assign PtrD = PopF | RepairD ? PtrM1 : PtrP1;
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assign PtrM1 = PtrQ - 1'b1;
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assign PtrP1 = PtrQ + 1'b1;
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// may have to handle a PushE and an incr at the same time.
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// *** what happens if jal is executing and there is a return being flushed in Decode?
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flopenr #(Depth) PTR(.clk(clk),
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@ -75,7 +74,7 @@ module RASPredictor
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always_ff @ (posedge clk) begin
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if(reset) begin
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for(index=0; index<StackSize; index++)
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memory[index] <= {`XLEN{1'b0}};
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memory[index] <= {`XLEN{1'b0}};
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end else if(PushE) begin
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memory[PtrP1] <= #1 PCLinkE;
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end
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@ -147,7 +147,7 @@ module bpred (
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// Part 3 RAS
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// *** need to add the logic to restore RAS on flushes. We will use incr for this.
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// *** needs to include flushX
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RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE,
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RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
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.PredInstrClassF, .InstrClassD, .InstrClassE,
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.WrongPredInstrClassD, .RASPCF, .PCLinkE);
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