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Some cleanup
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2d9de7b58f
commit
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18
src/cache/cache.sv
vendored
18
src/cache/cache.sv
vendored
@ -1,5 +1,5 @@
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///////////////////////////////////////////
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///////////////////////////////////////////
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// cache
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// cache.sv
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//
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Written: Ross Thompson ross1728@gmail.com
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// Created: 7 July 2021
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// Created: 7 July 2021
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@ -167,22 +167,22 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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// Adjust byte mask from word to cache line
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// Adjust byte mask from word to cache line
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onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded));
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onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded));
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for(index = 0; index < 2**LOGCWPL; index++) begin
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for(index = 0; index < 2**LOGCWPL; index++) begin
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assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
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assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
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end
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end
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assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1.
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assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1.
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// Merge write data into fetched cache line for store miss
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// Merge write data into fetched cache line for store miss
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for(index = 0; index < LINELEN/8; index++) begin
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for(index = 0; index < LINELEN/8; index++) begin
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mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
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mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
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.d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index]));
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.d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index]));
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end
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end
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assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
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assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
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end
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end
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else
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else
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begin:WriteSelLogic
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begin:WriteSelLogic
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// No need for this mux if the cache does not handle writes.
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// No need for this mux if the cache does not handle writes.
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assign LineWriteData = FetchBuffer;
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assign LineWriteData = FetchBuffer;
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assign LineByteMask = '1;
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assign LineByteMask = '1;
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end
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end
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Flush logic
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// Flush logic
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@ -203,8 +203,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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assign FlushWayFlag = FlushWay[NUMWAYS-1];
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assign FlushWayFlag = FlushWay[NUMWAYS-1];
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end // block: flushlogic
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end // block: flushlogic
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else begin:flushlogic
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else begin:flushlogic
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assign FlushWayFlag = 0;
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assign FlushWayFlag = 0;
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assign FlushAdrFlag = 0;
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assign FlushAdrFlag = 0;
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end
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end
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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4
src/cache/cacheLRU.sv
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4
src/cache/cacheLRU.sv
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@ -1,5 +1,5 @@
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///////////////////////////////////////////
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///////////////////////////////////////////
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// dcache (data cache)
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// cacheLRU.sv
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//
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Written: Ross Thompson ross1728@gmail.com
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// Created: 20 July 2021
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// Created: 20 July 2021
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@ -37,7 +37,7 @@ module cacheLRU
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input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant
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input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant
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input logic [NUMWAYS-1:0] HitWay, // Which way is valid and matches PAdr's tag
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input logic [NUMWAYS-1:0] HitWay, // Which way is valid and matches PAdr's tag
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input logic [NUMWAYS-1:0] ValidWay, // Which ways for a particular set are valid, ignores tag
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input logic [NUMWAYS-1:0] ValidWay, // Which ways for a particular set are valid, ignores tag
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input logic [SETLEN-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
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input logic [SETLEN-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
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input logic [SETLEN-1:0] PAdr, // Physical address
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input logic [SETLEN-1:0] PAdr, // Physical address
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input logic LRUWriteEn, // Update the LRU state
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input logic LRUWriteEn, // Update the LRU state
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input logic SetValid, // Set the dirty bit in the selected way and set
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input logic SetValid, // Set the dirty bit in the selected way and set
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4
src/cache/cachefsm.sv
vendored
4
src/cache/cachefsm.sv
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@ -1,11 +1,11 @@
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///////////////////////////////////////////
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///////////////////////////////////////////
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// dcache (data cache) fsm
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// cachefsm.sv
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//
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Written: Ross Thompson ross1728@gmail.com
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// Created: 25 August 2021
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// Created: 25 August 2021
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// Modified: 20 January 2023
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// Modified: 20 January 2023
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//
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//
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// Purpose: Controller for the dcache fsm
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// Purpose: Controller for the cache fsm
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//
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//
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// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1)
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// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1)
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//
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//
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5
src/cache/subcachelineread.sv
vendored
5
src/cache/subcachelineread.sv
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@ -1,11 +1,11 @@
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///////////////////////////////////////////
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///////////////////////////////////////////
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// subcachelineread
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// subcachelineread.sv
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//
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Written: Ross Thompson ross1728@gmail.com
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// Created: 4 February 2022
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// Created: 4 February 2022
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// Modified: 20 January 2023
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// Modified: 20 January 2023
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//
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//
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// Purpose: Muxes the cache line downto the word size. Also include possilbe save/restore registers/muxes.
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// Purpose: Muxes the cache line down to the word size. Also include possible save/restore registers/muxes.
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//
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//
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// Documentation: RISC-V System on Chip Design Chapter 7
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// Documentation: RISC-V System on Chip Design Chapter 7
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@ -31,7 +31,6 @@
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module subcachelineread #(parameter LINELEN, WORDLEN,
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module subcachelineread #(parameter LINELEN, WORDLEN,
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parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$
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parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$
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input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address
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input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address
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input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline
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input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline
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output logic [WORDLEN-1:0] ReadDataWord // read data of selected word.
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output logic [WORDLEN-1:0] ReadDataWord // read data of selected word.
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