Do file for riscvsingle

examples/verilog/riscvsingle/riscvsingle.do

@@ -0,0 +1,23 @@
+# riscvsingle.do 
+# David_Harris@hmc.edu 10 January 2021
+
+# compile, optimize, and start the simulation
+vlog riscvsingle.sv 
+vopt +acc work.testbench -o workopt 
+vsim workopt
+
+# Add waveforms and run the simulation
+add wave /testbench/clk
+add wave /testbench/reset
+add wave -divider "Main Datapath"
+add wave /testbench/dut/PC
+add wave /testbench/dut/Instr
+add wave /testbench/dut/rvsingle/dp/SrcA
+add wave /testbench/dut/rvsingle/dp/SrcB
+add wave /testbench/dut/rvsingle/dp/Result
+add wave -divider "Memory Bus"
+add wave /testbench/MemWrite
+add wave /testbench/DataAdr
+add wave /testbench/WriteData
+run -all
+view wave

examples/verilog/riscvsingle/riscvsingle.sv

@@ -334,7 +334,7 @@ module imem(input  logic [31:0] a,
   logic [31:0] RAM[63:0];
 
   initial
-      $readmemh("riscvtest.txt",RAM);
+      $readmemh("riscvtest.memfile",RAM);
 
   assign rd = RAM[a[31:2]]; // word aligned
 endmodule