From b76c371e451b50d42ffa9b107fe8c3f5ca8f8f17 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 18 Oct 2023 05:38:36 -0700 Subject: [PATCH 1/8] Config file cleanup --- config/rv32i/config.vh | 2 +- config/rv64i/config.vh | 2 +- sim/lint-wally | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 008687007..5c34ae413 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -36,7 +36,7 @@ localparam XLEN = 32'd32; localparam IEEE754 = 0; // I -localparam MISA = (32'h00000104); +localparam MISA = (32'h00000100); localparam ZICSR_SUPPORTED = 0; localparam ZIFENCEI_SUPPORTED = 0; localparam COUNTERS = 0; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 35fc2bdfa..ea668a45e 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -36,7 +36,7 @@ localparam XLEN = 32'd64; localparam IEEE754 = 0; // MISA RISC-V configuration per specification -localparam MISA = (32'h00000104); +localparam MISA = (32'h00000100); localparam ZICSR_SUPPORTED = 0; localparam ZIFENCEI_SUPPORTED = 0; localparam COUNTERS = 0; diff --git a/sim/lint-wally b/sim/lint-wally index 97bd2a877..263fb864f 100755 --- a/sim/lint-wally +++ b/sim/lint-wally @@ -16,7 +16,7 @@ done echo "All lints run with no errors or warnings" # --lint-only just runs lint rather than trying to compile and simulate -# -I points to the include directory where files such as `include wally-config.vh are found +# -I points to the include directory where files such as `include config.vh are found # For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command # Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist. From 48d42c1e7cc58565d6dfdb9c29e906718b00e1b3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 18 Oct 2023 05:50:41 -0700 Subject: [PATCH 2/8] Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates --- src/uncore/ahbapbbridge.sv | 1 - src/uncore/gpio_apb.sv | 11 +++-------- src/uncore/plic_apb.sv | 10 +++------- src/uncore/uart_apb.sv | 28 +++------------------------- 4 files changed, 9 insertions(+), 41 deletions(-) diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv index 381297f00..454f4d5df 100644 --- a/src/uncore/ahbapbbridge.sv +++ b/src/uncore/ahbapbbridge.sv @@ -88,7 +88,6 @@ module ahbapbbridge import cvw::*; #(parameter cvw_t P, int i; always_comb begin // default: no peripheral selected: read 0, indicate ready during access phase so bus doesn't hang - // *** also could assert ready right away HRDATA = 0; PREADYOUT = 1'b1; for (i=0; i Date: Wed, 18 Oct 2023 14:29:46 -0700 Subject: [PATCH 3/8] wrapper bug fix --- synthDC/scripts/wrapperGen.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/synthDC/scripts/wrapperGen.py b/synthDC/scripts/wrapperGen.py index aacdb0634..e931d0a65 100755 --- a/synthDC/scripts/wrapperGen.py +++ b/synthDC/scripts/wrapperGen.py @@ -43,7 +43,7 @@ index=0 # string copy logic for l in lines: - if l.find("module") == 0: + if l.lstrip().find("module") == 0: lineModuleStart = index moduleName = l.split()[1] writeBuf = True @@ -51,7 +51,7 @@ for l in lines: continue if (writeBuf): buf += l - if l.find (");") == 0: + if l.lstrip().find (");") == 0: lineModuleEnd = index break index+=1 @@ -64,6 +64,7 @@ wrapperPath = f"{os.getenv('WALLY')}/synthDC/wrappers/{moduleName}wrapper.sv" # clear wrappers directory os.system(f"rm {os.getenv('WALLY')}/synthDC/wrappers/*") +os.system(f"mkdir {os.getenv('WALLY')}/synthDC/wrappers") fout = open(wrapperPath, "w") From 7c1606264a365e94a6de0911bb9ac5d747d4aaf1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 19 Oct 2023 06:16:52 -0700 Subject: [PATCH 4/8] Adjusted synthesis scripts to report on DESIGN even when a wrapper is used --- .gitignore | 1 + synthDC/scripts/synth.tcl | 15 +++++++++++---- synthDC/wallySynth.py | 2 +- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/.gitignore b/.gitignore index 41ccba5f9..04ae44109 100644 --- a/.gitignore +++ b/.gitignore @@ -82,6 +82,7 @@ synthDC/ppa/plots synthDC/wallyplots/ synthDC/runArchive synthDC/hdl +synthDC/wrappers sim/power.saif tests/fp/vectors/*.tv synthDC/Summary.csv diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 075bb5db9..00800a7ef 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -53,6 +53,7 @@ if { $wrapper == 1 } { } else { set my_toplevel $::env(DESIGN) } +set my_design $::env(DESIGN) # Set number of significant digits set report_default_significant_digits 6 @@ -238,6 +239,12 @@ set write_rep 1 ;# generates estimated area and timing report set write_cst 1 ;# generate report of constraints set write_hier 1 ;# generate hierarchy report +# Report on DESIGN, not wrapper. However, design has a suffix for the parameters. +if { $wrapper == 1 } { + set designname [format "%s%s" $my_design "__*"] + current_design $designname +} + # Report Constraint Violators set filename [format "%s%s" $outputDir "/reports/constraint_all_violators.rpt"] redirect $filename {report_constraint -all_violators} @@ -246,16 +253,16 @@ redirect $filename {report_constraint -all_violators} redirect $outputDir/reports/check_design.rpt { check_design } # Report Final Netlist (Hierarchical) -set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sv"] +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sv"] write_file -f verilog -hierarchy -output $filename -set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdc"] +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdc"] write_sdc $filename -set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".ddc"] +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".ddc"] write_file -format ddc -hierarchy -o $filename -set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdf"] +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_design ".sdf"] write_sdf $filename # QoR diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 139bcdd60..141b6e8c5 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -7,7 +7,7 @@ import argparse def runSynth(config, mod, tech, freq, maxopt, usesram): global pool - command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram) + command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1 WRAPPER=1".format(config, mod, tech, freq, maxopt, usesram) pool.map(mask, [command]) def mask(command): From 348e74b8bea796efeeeeeb2f1c0186e91fe7831a Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 19 Oct 2023 10:44:03 -0700 Subject: [PATCH 5/8] Updated wrapper generation to be automatic without specifying WRAPPER=1; instead looks for cvw_t in the file. Also starting to add OSU 130 nm synthesis. --- bin/libppa.pl | 14 ++++++++++++-- bin/wally-tool-chain-install.sh | 4 ++++ synthDC/Makefile | 9 +-------- synthDC/scripts/synth.tcl | 10 ++++++---- synthDC/scripts/wrapperGen.py | 6 +++--- 5 files changed, 26 insertions(+), 17 deletions(-) diff --git a/bin/libppa.pl b/bin/libppa.pl index 56b3702dd..ccf4f1548 100755 --- a/bin/libppa.pl +++ b/bin/libppa.pl @@ -41,6 +41,16 @@ my @cr; my @cf; my @rt; my @ft; # cell and corners to analyze my $libpath; my $libbase; my $cellname; my @corners; +# Sky130 +$libpath ="/opt/riscv/cad/lib/sky130_osu_sc_t12/12T_ms/lib"; +$libbase = "sky130_osu_sc_12T_ms_"; +$cellname = "sky130_osu_sc_12T_ms__inv_1"; +@corners = ("TT_1P8_25C.ccs", "tt_1P80_25C.ccs", "tt_1P62_25C.ccs", "tt_1P89_25C.ccs", "ss_1P60_-40C.ccs", "ss_1P60_100C.ccs", "ss_1P60_150C.ccs", "ff_1P95_-40C.ccs", "ff_1P95_100C.ccs", "ff_1P95_150C.ccs"); +printf("Library $libbase Cell $cellname\n"); +foreach my $corner (@corners) { + &analyzeCell($corner); +} + # Sky90 $libpath ="/opt/riscv/cad/lib/sky90/sky90_sc/V1.7.4/lib"; $libbase = "scc9gena_"; @@ -54,7 +64,7 @@ foreach my $corner (@corners) { # TSMC $libpath = "/proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a"; $libbase = "tcbn28hpcplusbwp30p140"; -$cellname = "INVD1..."; // replace this with the full name of the library cell +$cellname = "INVD1..."; # replace this with the full name of the library cell @corners = ("tt0p9v25c", "tt0p8v25c", "tt1v25c", "tt0p9v85c", "ssg0p9vm40c", "ssg0p9v125c", "ssg0p81vm40c", "ssg0p81v125c", "ffg0p88vm40c", "ffg0p88v125c", "ffg0p99vm40c", "ffg0p99v125c"); printf("\nLibrary $libbase Cell $cellname\n"); foreach my $corner (@corners) { @@ -129,7 +139,7 @@ sub analyzeCell { my $delay = &computeDelay($cap); my $cornerr = sprintf("%20s", $corner); my $delayr = sprintf("%2.1f", $delay*1000); - my $leakager = sprintf("%3.1f", $leakage); + my $leakager = sprintf("%3.3f", $leakage); print("$cornerr: Delay $delayr Leakage: $leakager capacitance: $cap\n"); #print("$cellname $corner: Area $area Leakage: $leakage capacitance: $cap delay $delay\n"); diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 7ff470f17..26dd54c8d 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -167,3 +167,7 @@ sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 sudo pip3 install testresources pip3 install git+https://github.com/riscv/riscof.git +# Download OSU Skywater 130 cell library +sudo mkdir -p $RISCV/cad/lib +cd $RISCV/cad/lib +sudo git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 diff --git a/synthDC/Makefile b/synthDC/Makefile index 57b478795..8cbfb934e 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -17,11 +17,9 @@ export TECH ?= sky90 export MAXCORES ?= 1 # MAXOPT turns on flattening, boundary optimization, and retiming # The output netlist is hard to interpret, but significantly better PPA -# WRAPPER turns on wrapper generation export MAXOPT ?= 0 export DRIVE ?= FLOP export USESRAM ?= 0 -export WRAPPER ?= 0 time := $(shell date +%F-%H-%M) @@ -120,11 +118,6 @@ ifeq ($(SAIFPOWER), 1) cp -f ../sim/power.saif . endif - -mkwrapper: -ifeq ($(WRAPPER),1) - python3 $(WALLY)/synthDC/scripts/wrapperGen.py $(DESIGN) -endif mkdirecs: @echo "DC Synthesis" @mkdir -p $(OUTPUTDIR) @@ -134,7 +127,7 @@ mkdirecs: @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped -synth: mkwrapper mkdirecs configs rundc # clean +synth: mkdirecs configs rundc # clean rundc: ifeq ($(TECH), tsmc28psyn) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 00800a7ef..542cb8fc1 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -24,18 +24,20 @@ set hdl_src "../src" set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) set drive $::env(DRIVE) -set wrapper $::env(WRAPPER) eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/} -#eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} -if {$wrapper ==1 } { + +# Check if a wrapper is needed (when cvw_t parameters are used) +set wrapper 0 +if {[eval exec grep "cvw_t" {$outputDir/hdl/$::env(DESIGN).sv}] ne ""} { + set wrapper 1 + exec python3 $::env(WALLY)/synthDC/scripts/wrapperGen.py $::env(DESIGN) eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/} } - # Only for FMA class project; comment out when done # eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/} diff --git a/synthDC/scripts/wrapperGen.py b/synthDC/scripts/wrapperGen.py index e931d0a65..d830f5155 100755 --- a/synthDC/scripts/wrapperGen.py +++ b/synthDC/scripts/wrapperGen.py @@ -63,8 +63,8 @@ buf += f"\t{moduleName} #(P) dut(.*);\nendmodule" wrapperPath = f"{os.getenv('WALLY')}/synthDC/wrappers/{moduleName}wrapper.sv" # clear wrappers directory -os.system(f"rm {os.getenv('WALLY')}/synthDC/wrappers/*") -os.system(f"mkdir {os.getenv('WALLY')}/synthDC/wrappers") +os.system(f"rm -f {os.getenv('WALLY')}/synthDC/wrappers/*") +os.system(f"mkdir -p {os.getenv('WALLY')}/synthDC/wrappers") fout = open(wrapperPath, "w") @@ -75,4 +75,4 @@ fout.close() -print(buf) \ No newline at end of file +#print(buf) \ No newline at end of file From 8f717c325493b7ddda1fd5333bfb2f4e9ca22494 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 19 Oct 2023 10:49:06 -0700 Subject: [PATCH 6/8] Removed wrapper from wallySynth because it is automatic now --- synthDC/wallySynth.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index 141b6e8c5..139bcdd60 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -7,7 +7,7 @@ import argparse def runSynth(config, mod, tech, freq, maxopt, usesram): global pool - command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1 WRAPPER=1".format(config, mod, tech, freq, maxopt, usesram) + command = "make synth DESIGN=wallypipelinedcore CONFIG={} MOD={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} USESRAM={} MAXCORES=1".format(config, mod, tech, freq, maxopt, usesram) pool.map(mask, [command]) def mask(command): From 6e7c0547a1eeebd142d310891f844115e9b6e55f Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 19 Oct 2023 11:16:02 -0700 Subject: [PATCH 7/8] Modified log2 coding to avoid synthesis warning --- src/cache/cacheLRU.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 34ea59612..613dd6de7 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -70,8 +70,10 @@ module cacheLRU // coverage off // Excluded from coverage b/c it is untestable without varying NUMWAYS. function integer log2 (integer value); - for (log2=0; value>0; log2=log2+1) - value = value>>1; + int val; + val = value; + for (log2 = 0; val > 0; log2 = log2+1) + val = val >> 1; return log2; endfunction // log2 // coverage on From cbf0c01fd69f3b8afd790b0695eb925c3bd2f07c Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 19 Oct 2023 13:46:30 -0700 Subject: [PATCH 8/8] Set drive for Sky130 --- synthDC/scripts/synth.tcl | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 542cb8fc1..bdd868dd1 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -148,18 +148,22 @@ set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]] # Setting constraints on input ports if {$tech == "sky130"} { - set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk + if {$drive == "INV"} { + set_driving_cell -lib_cell inv -pin Y $all_in_ex_clk + } elseif {$drive == "FLOP"} { + set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk + } } elseif {$tech == "sky90"} { if {$drive == "INV"} { - set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk + set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk } elseif {$drive == "FLOP"} { - set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk + set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk } } elseif {$tech == "tsmc28" || $tech=="tsmc28psyn"} { if {$drive == "INV"} { - set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk + set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk } elseif {$drive == "FLOP"} { - set_driving_cell -lib_cell DFQD1BWP30P140 -pin Q $all_in_ex_clk + set_driving_cell -lib_cell DFQD1BWP30P140 -pin Q $all_in_ex_clk } } @@ -174,16 +178,20 @@ if {$drive == "FLOP"} { # Setting load constraint on output ports if {$tech == "sky130"} { - set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] -} elseif {$tech == "sky90"} { if {$drive == "INV"} { - set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs] + set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__inv_4/A] * 1] [all_outputs] + } elseif {$drive == "FLOP"} { + set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] + } + } elseif {$tech == "sky90"} { + if {$drive == "INV"} { + set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs] } elseif {$drive == "FLOP"} { set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] } } elseif {$tech == "tsmc28" || $tech == "tsmc28psyn"} { if {$drive == "INV"} { - set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs] + set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs] } elseif {$drive == "FLOP"} { set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/DFQD1BWP30P140/D] * 1] [all_outputs] }