made redunantmul generate DW02_multp for synopsys sythnesis

wally-pipelined/config/rv32g/wally-config.vh

@@ -30,6 +30,7 @@
 `define QEMU 0
 `define BUILDROOT 0
 `define BUSYBEAR 0
+`define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 32

wally-pipelined/config/rv32ic/wally-config.vh

@@ -30,6 +30,7 @@
 `define QEMU 0
 `define BUILDROOT 0
 `define BUSYBEAR 0
+`define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 32

wally-pipelined/config/rv64BP/wally-config.vh

@@ -31,6 +31,7 @@
 `define QEMU 0
 `define BUILDROOT 0
 `define BUSYBEAR 0
+`define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64

wally-pipelined/config/rv64g/wally-config.vh

@@ -30,6 +30,7 @@
 `define QEMU 0
 `define BUILDROOT 0
 `define BUSYBEAR 0
+`define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64

wally-pipelined/config/rv64ic/wally-config.vh

@@ -30,6 +30,7 @@
 `define QEMU 0
 `define BUILDROOT 0
 `define BUSYBEAR 0
+`define DESIGN_COMPILER 0
 
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64

wally-pipelined/src/muldiv/redundantmul.sv

@@ -25,16 +25,19 @@
 
 `include "wally-config.vh"
 
-/* verilator lint_off UNOPTFLAT */
-
 module redundantmul #(parameter WIDTH =8)(
   input  logic [WIDTH-1:0] a,b,
   output logic [2*WIDTH-1:0] out0, out1);
 
-  assign out0 = 0;
+  generate 
-  assign out1 = a*b;
+    if (`DESIGN_COMPILER == 1) 
-    // DW02_multp #(`XLEN, `XLEN, 2*`XLEN) bigmul(.a(Aprime), .b(Bprime), .tc(1'b0), .out0(PP0E), .out1(PP1E));
+        DW02_multp #(WIDTH, WIDTH, 2*WIDTH) bigmul(.a, .b, .tc(1'b0), .out0, .out1);
+    else begin
+      assign out0 = 0;
+      assign out1 = a*b;
+    end 
+  endgenerate
 
 endmodule
 
-/* verilator lint_on UNOPTFLAT */
+