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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Lint cleanup
This commit is contained in:
parent
5f1ee1ac85
commit
0ab3f28991
@ -12,7 +12,7 @@ NC='\033[0m' # No Color
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fails=0
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fails=0
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if [ "$1" == "--nightly" ]; then
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if [ "$1" == "--nightly" ]; then
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i)
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derivconfigs=`ls $WALLY/config/deriv`
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derivconfigs=`ls $WALLY/config/deriv`
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for entry in $derivconfigs
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for entry in $derivconfigs
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do
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do
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@ -21,7 +21,7 @@ if [ "$1" == "--nightly" ]; then
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fi
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fi
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done
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done
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else
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else
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i ) # add fdqh_rv64gc when working
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configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc)
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fi
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fi
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for config in ${configs[@]}; do
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for config in ${configs[@]}; do
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@ -388,10 +388,23 @@ VIRTMEM_SUPPORTED 0
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deriv nodcache_rv32gc rv32gc
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deriv nodcache_rv32gc rv32gc
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DCACHE_SUPPORTED 0
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DCACHE_SUPPORTED 0
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D_SUPPORTED 0
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ZALRSC_SUPPORTED 0
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ZAAMO_SUPPORTED 0
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ZICBOM_SUPPORTED 0
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ZICBOZ_SUPPORTED 0
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VIRTMEM_SUPPORTED 0
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# nocache_rv32gc must also disable several features incompatible with no cache
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deriv nocache_rv32gc rv32gc
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deriv nocache_rv32gc rv32gc
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ICACHE_SUPPORTED 0
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ICACHE_SUPPORTED 0
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DCACHE_SUPPORTED 0
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DCACHE_SUPPORTED 0
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D_SUPPORTED 0
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ZALRSC_SUPPORTED 0
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ZAAMO_SUPPORTED 0
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ZICBOM_SUPPORTED 0
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ZICBOZ_SUPPORTED 0
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VIRTMEM_SUPPORTED 0
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deriv noicache_rv64gc rv64gc
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deriv noicache_rv64gc rv64gc
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ICACHE_SUPPORTED 0
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ICACHE_SUPPORTED 0
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@ -43,7 +43,7 @@ module zknde64 import cvw::*; #(parameter cvw_t P) (
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aes64e aes64e(.rs1(A), .rs2(B), .finalround(ZKNSelect[2]), .Sbox0Out, .SboxEIn, .result(aes64eRes));
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aes64e aes64e(.rs1(A), .rs2(B), .finalround(ZKNSelect[2]), .Sbox0Out, .SboxEIn, .result(aes64eRes));
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mux2 #(32) sboxmux(SboxEIn, SboxKIn, ZKNSelect[1], Sbox0In);
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mux2 #(32) sboxmux(SboxEIn, SboxKIn, ZKNSelect[1], Sbox0In);
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end else begin
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end else begin
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assign aes64dRes = '0;
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assign aes64eRes = '0;
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assign Sbox0In = SboxKIn;
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assign Sbox0In = SboxKIn;
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end
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end
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@ -144,7 +144,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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logic DTLBMissM; // DTLB miss causes HPTW walk
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logic DTLBMissM; // DTLB miss causes HPTW walk
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logic DTLBWriteM; // Writes PTE and PageType to DTLB
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logic DTLBWriteM; // Writes PTE and PageType to DTLB
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logic DataUpdateDAM; // DTLB hit needs to update dirty or access bits
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logic LSULoadAccessFaultM; // Load acces fault
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logic LSULoadAccessFaultM; // Load acces fault
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logic LSUStoreAmoAccessFaultM; // Store access fault
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logic LSUStoreAmoAccessFaultM; // Store access fault
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logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle
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logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle
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@ -194,7 +193,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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if(P.VIRTMEM_SUPPORTED) begin : hptw
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if(P.VIRTMEM_SUPPORTED) begin : hptw
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hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrUpdateAF, .ITLBWriteF,
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hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrUpdateAF, .ITLBWriteF,
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.DTLBMissOrUpdateDAM, .DTLBWriteM, .DataUpdateDAM,
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.DTLBMissOrUpdateDAM, .DTLBWriteM,
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.FlushW, .DCacheBusStallM, .SATP_REGW, .PCSpillF,
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.FlushW, .DCacheBusStallM, .SATP_REGW, .PCSpillF,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_ADUE, .PrivilegeModeW,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_ADUE, .PrivilegeModeW,
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.ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
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.ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
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@ -236,6 +235,8 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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if(P.ZICSR_SUPPORTED == 1) begin : dmmu
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if(P.ZICSR_SUPPORTED == 1) begin : dmmu
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logic DisableTranslation; // During HPTW walk or D$ flush disable virtual memory address translation
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logic DisableTranslation; // During HPTW walk or D$ flush disable virtual memory address translation
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logic WriteAccessM;
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logic WriteAccessM;
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logic DataUpdateDAM; // DTLB hit needs to update dirty or access bits
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assign DisableTranslation = SelHPTW | FlushDCacheM;
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assign DisableTranslation = SelHPTW | FlushDCacheM;
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assign WriteAccessM = PreLSURWM[0];
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assign WriteAccessM = PreLSURWM[0];
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mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))
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mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))
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@ -49,7 +49,6 @@ module hptw import cvw::*; #(parameter cvw_t P) (
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input logic ITLBMissOrUpdateAF,
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input logic ITLBMissOrUpdateAF,
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input logic DTLBMissOrUpdateDAM,
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input logic DTLBMissOrUpdateDAM,
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input logic FlushW,
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input logic FlushW,
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input logic DataUpdateDAM,
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output logic [P.XLEN-1:0] PTE, // page table entry to TLBs
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output logic [P.XLEN-1:0] PTE, // page table entry to TLBs
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output logic [1:0] PageType, // page type to TLBs
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output logic [1:0] PageType, // page type to TLBs
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output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
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output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry
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