From 0a5b500aca7a69c6d6b6bb9bd6dcfb31d015cd24 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 30 Mar 2022 11:38:25 -0500 Subject: [PATCH] Changed sram1p1rw to have the same type of bytewrite enables as bram. --- pipelined/src/cache/sram1p1rw.sv | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/pipelined/src/cache/sram1p1rw.sv b/pipelined/src/cache/sram1p1rw.sv index 5ecb7374a..94ec7ce80 100644 --- a/pipelined/src/cache/sram1p1rw.sv +++ b/pipelined/src/cache/sram1p1rw.sv @@ -47,7 +47,8 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( always_ff @(posedge clk) AdrD <= Adr; - genvar index; + integer index; +/* -----\/----- EXCLUDED -----\/----- for(index = 0; index < WIDTH/8; index++) begin always_ff @(posedge clk) begin if (WriteEnable & ByteMask[index]) begin @@ -55,6 +56,18 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( end end end + -----/\----- EXCLUDED -----/\----- */ + + always_ff @(posedge clk) begin + if (WriteEnable) begin + for(index = 0; index < WIDTH/8; index++) begin + if(ByteMask[index]) begin + StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8]; + end + end + end + end + // if not a multiple of 8, MSByte is not 8 bits long. if(WIDTH%8 != 0) begin always_ff @(posedge clk) begin