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Remove unused signals

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This commit is contained in:
David Harris 2023-01-07 05:46:22 -08:00
parent 6d22c73676
commit 0a011f4548
5 changed files with 2 additions and 7 deletions
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2
pipelined/src/ieu/controller.sv
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@ -103,7 +103,7 @@ module controller(
logic SubArithD; logic SubArithD;
logic subD, sraD, sltD, sltuD; logic subD, sraD, sltD, sltuD;
logic BranchTakenE; logic BranchTakenE;
logic eqE, ltE, ltuE; logic eqE, ltE;
logic unused; logic unused;
logic BranchFlagE; logic BranchFlagE;
logic IEURegWriteE; logic IEURegWriteE;

1
pipelined/src/ieu/datapath.sv
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@ -62,7 +62,6 @@ module datapath (
input logic [2:0] ResultSrcW, input logic [2:0] ResultSrcW,
input logic [`XLEN-1:0] FCvtIntResW, input logic [`XLEN-1:0] FCvtIntResW,
input logic [`XLEN-1:0] ReadDataW, input logic [`XLEN-1:0] ReadDataW,
// input logic [`XLEN-1:0] PCLinkW,
input logic [`XLEN-1:0] CSRReadValW, MDUResultW, input logic [`XLEN-1:0] CSRReadValW, MDUResultW,
input logic [`XLEN-1:0] FPIntDivResultW, input logic [`XLEN-1:0] FPIntDivResultW,
// Hazard Unit signals // Hazard Unit signals

1
pipelined/src/ieu/ieu.sv
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@ -63,7 +63,6 @@ module ieu (
input logic [`XLEN-1:0] FCvtIntResW, input logic [`XLEN-1:0] FCvtIntResW,
output logic [4:0] RdW, output logic [4:0] RdW,
input logic [`XLEN-1:0] ReadDataW, input logic [`XLEN-1:0] ReadDataW,
// input logic [`XLEN-1:0] PCLinkW,
output logic InstrValidM, output logic InstrValidM,
// hazards // hazards
input logic StallD, StallE, StallM, StallW, input logic StallD, StallE, StallM, StallW,

3
pipelined/src/ifu/ifu.sv
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@ -52,7 +52,6 @@ module ifu (
output logic [`XLEN-1:0] PCE, output logic [`XLEN-1:0] PCE,
output logic BPPredWrongE, output logic BPPredWrongE,
// Mem // Mem
input logic RetM, TrapM,
output logic CommittedF, output logic CommittedF,
input logic [`XLEN-1:0] UnalignedPCNextF, input logic [`XLEN-1:0] UnalignedPCNextF,
output logic [`XLEN-1:0] PCNext2F, output logic [`XLEN-1:0] PCNext2F,
@ -248,11 +247,9 @@ module ifu (
.s({SelIROM, ~CacheableF}), .y(InstrRawF[31:0])); .s({SelIROM, ~CacheableF}), .y(InstrRawF[31:0]));
end else begin : passthrough end else begin : passthrough
assign IFUHADDR = PCPF; assign IFUHADDR = PCPF;
logic CaptureEn;
logic [31:0] FetchBuffer; logic [31:0] FetchBuffer;
logic [1:0] BusRW; logic [1:0] BusRW;
assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : '0; assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : '0;
// assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{SelIROM, SelIROM};
assign IFUHSIZE = 3'b010; assign IFUHSIZE = 3'b010;
ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY), ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY),

2
pipelined/src/wally/wallypipelinedcore.sv
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@ -183,7 +183,7 @@ module wallypipelinedcore (
.BPPredWrongE, .BPPredWrongE,
// Mem // Mem
.RetM, .TrapM, .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
.InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM,
.BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,