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updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well

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Noah Limpert 2021-11-24 23:22:04 -08:00
parent 93b626ce2a
commit 09d3322a26
1 changed files with 81 additions and 64 deletions
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145
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -196,81 +196,81 @@ module wallypipelinedhart (
ieu ieu( ieu ieu(
.clk, .reset, .clk, .reset,
// Decode Stage interface // Decode Stage interface
.InstrD, .IllegalIEUInstrFaultD, .InstrD, .IllegalIEUInstrFaultD,
.IllegalBaseInstrFaultD, .IllegalBaseInstrFaultD,
// Execute Stage interface // Execute Stage interface
.PCE, .PCLinkE, .FWriteIntE, .IllegalFPUInstrE, .PCE, .PCLinkE, .FWriteIntE, .IllegalFPUInstrE,
.FWriteDataE, .PCTargetE, .MulDivE, .W64E, .FWriteDataE, .PCTargetE, .MulDivE, .W64E,
.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
.SrcAE, .SrcBE, .FWriteIntM, .SrcAE, .SrcBE, .FWriteIntM,
// Memory stage interface // Memory stage interface
.SquashSCW, // from LSU .SquashSCW, // from LSU
.MemRWM, // read/write control goes to LSU .MemRWM, // read/write control goes to LSU
.AtomicE, // atomic control goes to LSU .AtomicE, // atomic control goes to LSU
.AtomicM, // atomic control goes to LSU .AtomicM, // atomic control goes to LSU
.MemAdrM, .MemAdrE, .WriteDataM, // Address and write data to LSU .MemAdrM, .MemAdrE, .WriteDataM, // Address and write data to LSU
.Funct3M, // size and signedness to LSU .Funct3M, // size and signedness to LSU
.SrcAM, // to privilege and fpu .SrcAM, // to privilege and fpu
.RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
// Writeback stage // Writeback stage
.CSRReadValW, .ReadDataM, .MulDivResultW, .CSRReadValW, .ReadDataM, .MulDivResultW,
.FWriteIntW, .RdW, .ReadDataW, .FWriteIntW, .RdW, .ReadDataW,
.InstrValidM, .InstrValidM,
// hazards // hazards
.StallD, .StallE, .StallM, .StallW, .StallD, .StallE, .StallM, .StallW,
.FlushD, .FlushE, .FlushM, .FlushW, .FlushD, .FlushE, .FlushM, .FlushW,
.FPUStallD, .LoadStallD, .MulDivStallD, .CSRRdStallD, .FPUStallD, .LoadStallD, .MulDivStallD, .CSRRdStallD,
.PCSrcE, .PCSrcE,
.CSRReadM, .CSRWriteM, .PrivilegedM, .CSRReadM, .CSRWriteM, .PrivilegedM,
.CSRWritePendingDEM, .StoreStallD .CSRWritePendingDEM, .StoreStallD
); // integer execution unit: integer register file, datapath and controller ); // integer execution unit: integer register file, datapath and controller
lsu lsu( lsu lsu(
.clk, .reset, .StallM, .FlushM, .StallW, .clk, .reset, .StallM, .FlushM, .StallW,
.FlushW, .FlushW,
// CPU interface // CPU interface
.MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
.AtomicM, .ExceptionM, .PendingInterruptM, .AtomicM, .ExceptionM, .PendingInterruptM,
.CommittedM, .DCacheMiss, .DCacheAccess, .CommittedM, .DCacheMiss, .DCacheAccess,
.SquashSCW, .SquashSCW,
//.DataMisalignedM(DataMisalignedM), //.DataMisalignedM(DataMisalignedM),
.MemAdrE, .MemAdrM, .WriteDataM, .MemAdrE, .MemAdrM, .WriteDataM,
.ReadDataM, .FlushDCacheM, .ReadDataM, .FlushDCacheM,
// connected to ahb (all stay the same) // connected to ahb (all stay the same)
.DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck, .DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck,
.DCfromAHBReadData, .DCtoAHBWriteData, .DCtoAHBSizeM, .DCfromAHBReadData, .DCtoAHBWriteData, .DCtoAHBSizeM,
// connect to csr or privilege and stay the same. // connect to csr or privilege and stay the same.
.PrivilegeModeW, // connects to csr .PrivilegeModeW, // connects to csr
.PMPCFG_ARRAY_REGW, // connects to csr .PMPCFG_ARRAY_REGW, // connects to csr
.PMPADDR_ARRAY_REGW, // connects to csr .PMPADDR_ARRAY_REGW, // connects to csr
// hptw keep i/o // hptw keep i/o
.SATP_REGW, // from csr .SATP_REGW, // from csr
.STATUS_MXR, // from csr .STATUS_MXR, // from csr
.STATUS_SUM, // from csr .STATUS_SUM, // from csr
.STATUS_MPRV, // from csr .STATUS_MPRV, // from csr
.STATUS_MPP, // from csr .STATUS_MPP, // from csr
.DTLBFlushM, // connects to privilege .DTLBFlushM, // connects to privilege
.DTLBLoadPageFaultM, // connects to privilege .DTLBLoadPageFaultM, // connects to privilege
.DTLBStorePageFaultM, // connects to privilege .DTLBStorePageFaultM, // connects to privilege
.LoadMisalignedFaultM, // connects to privilege .LoadMisalignedFaultM, // connects to privilege
.LoadAccessFaultM, // connects to privilege .LoadAccessFaultM, // connects to privilege
.StoreMisalignedFaultM, // connects to privilege .StoreMisalignedFaultM, // connects to privilege
.StoreAccessFaultM, // connects to privilege .StoreAccessFaultM, // connects to privilege
.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF,
.WalkerInstrPageFaultF, .WalkerLoadPageFaultM, .WalkerInstrPageFaultF, .WalkerLoadPageFaultM,
.WalkerStorePageFaultM, .WalkerStorePageFaultM,
.LSUStall); // change to LSUStall .LSUStall); // change to LSUStall
@ -354,6 +354,23 @@ module wallypipelinedhart (
); );
fpu fpu(.*); // floating point unit fpu fpu(
.clk, .reset,
.FRM_REGW, // Rounding mode from CSR
.InstrD, // instruction from IFU
.ReadDataW,// Read data from memory
.SrcAE, // Integer input being processed (from IEU)
.StallE, .StallM, .StallW, // stall signals from HZU
.FlushE, .FlushM, .FlushW, // flush signals from HZU
.RdM, .RdW, // which FP register to write to (from IEU)
.FRegWriteM, // FP register write enable
.FStallD, // Stall the decode stage
.FWriteIntE, .FWriteIntM, .FWriteIntW, // integer register write enable
.FWriteDataE, // Data to be written to memory
.FIntResM, // data to be written to integer register
.FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
.IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
.SetFflagsM // FPU flags (to privileged unit)
); // floating point unit
endmodule endmodule