makefile bug fix

synthDC/Makefile

@@ -24,7 +24,6 @@ export USESRAM ?= 0
 export WRAPPER ?= 0
 
 ifeq ($(WRAPPER),1)
-	rm $(WALLY)/synthDC/wrappers/*
 	NAME := synthWrapper
 else 
 	NAME := synth
@@ -160,4 +159,4 @@ clean:
 	rm -f power.saif
 	rm -f Synopsys_stack_trace_*.txt
 	rm -f crte_*.txt
-	rm $(WALLY)/synthDC/wrappers/*
+	rm $(WALLY)/synthDC/wrappers/*

synthDC/scripts/wrapperGen.py

@@ -63,7 +63,7 @@ buf += f"\t{moduleName} #(P) dut(.*);\nendmodule"
 wrapperPath = f"{os.getenv('WALLY')}/synthDC/wrappers/{moduleName}wrapper.sv"
 
 # clear wrappers directory 
-os.system(f"rm {os.getenv('WALLY')}/src/wrappers/*")
+os.system(f"rm {os.getenv('WALLY')}/synthDC/wrappers/*")
 
 fout = open(wrapperPath, "w")
 

synthDC/wrappers/wallypipelinedcorewrapper.sv

@@ -1,24 +0,0 @@
-import cvw::*;
-`include "config.vh"
-`include "parameter-defs.vh"
-module wallypipelinedcorewrapper (
-   input  logic                  clk, reset,
-   // Privileged
-   input  logic                  MTimerInt, MExtInt, SExtInt, MSwInt,
-   input  logic [63:0]           MTIME_CLINT, 
-   // Bus Interface
-   input  logic [P.AHBW-1:0]     HRDATA,
-   input  logic                  HREADY, HRESP,
-   output logic                  HCLK, HRESETn,
-   output logic [P.PA_BITS-1:0]  HADDR,
-   output logic [P.AHBW-1:0]     HWDATA,
-   output logic [P.XLEN/8-1:0]   HWSTRB,
-   output logic                  HWRITE,
-   output logic [2:0]            HSIZE,
-   output logic [2:0]            HBURST,
-   output logic [3:0]            HPROT,
-   output logic [1:0]            HTRANS,
-   output logic                  HMASTLOCK
-);
-	wallypipelinedcore #(P) dut(.*);
-endmodule