From 906e74dac231535ffb5ddc6ea0672c7597775eb0 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 28 Feb 2023 15:03:59 -0800
Subject: [PATCH 1/2] Pulled to latest commit of riscv-arch-test

---
 addins/riscv-arch-test | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index ee028eb32..a3b7f0c2c 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit ee028eb325525148a34420a4ca7959b24220a91e
+Subproject commit a3b7f0c2cf89652b8a0cba3146890c512ff8ba44

From f86a12f282847f0e389a73d8dfb8d8800e50ab25 Mon Sep 17 00:00:00 2001
From: eroom1966 <moore@imperas.com>
Date: Wed, 1 Mar 2023 15:37:11 +0000
Subject: [PATCH 2/2] update testbench for memory privileges also update
 configuration to define value of mimpid

---
 sim/imperas.ic                 |  7 +++++
 testbench/testbench_imperas.sv | 57 +++++++++++++++++++++++++++++-----
 2 files changed, 56 insertions(+), 8 deletions(-)

diff --git a/sim/imperas.ic b/sim/imperas.ic
index d28234bbc..69d57f702 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -1,3 +1,7 @@
+#--showoverrides
+#--help --helpall
+--traceregs
+
 --override cpu/show_c_prefix=T
 --override cpu/unaligned=F
 --override cpu/ignore_non_leaf_DAU=1
@@ -33,3 +37,6 @@
 
 # ignore settings of bits DAU for non leaf page table walks
 --override cpu/ignore_non_leaf_DAU=1
+
+# mimpid = 0x100
+--override cpu/mimpid=0x100
diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
index f26339007..cbca49275 100644
--- a/testbench/testbench_imperas.sv
+++ b/testbench/testbench_imperas.sv
@@ -137,7 +137,12 @@ module testbench;
                 .CMP_CSR     (1)
                ) idv_trace2api(rvvi);
 
+    int PRIV_RWX = RVVI_MEMORY_PRIVILEGE_READ | RVVI_MEMORY_PRIVILEGE_WRITE | RVVI_MEMORY_PRIVILEGE_EXEC;
+    int PRIV_RW  = RVVI_MEMORY_PRIVILEGE_READ | RVVI_MEMORY_PRIVILEGE_WRITE;
+    int PRIV_X   =                                                            RVVI_MEMORY_PRIVILEGE_EXEC;
+
     initial begin 
+      
       MAX_ERRS = 3;
 
       // Initialize REF (do this before initializing the DUT)
@@ -158,6 +163,41 @@ module testbench;
       void'(rvviRefCsrSetVolatile(0, 32'hC02));   // INSTRET
       void'(rvviRefCsrSetVolatile(0, 32'hB02));   // MINSTRET
       void'(rvviRefCsrSetVolatile(0, 32'hC01));   // TIME
+      
+      // cannot predict this register due to latency between
+      // pending and taken
+      void'(rvviRefCsrSetVolatile(0, 32'h344));
+      rvviRefCsrCompareEnable(0, 32'h344, RVVI_FALSE);
+      
+      // Memory lo, hi, priv (RVVI_MEMORY_PRIVILEGE_{READ,WRITE,EXEC})
+      void'(rvviRefMemorySetPrivilege(56'h0, 56'h7fffffffff, 0));
+      if (`BOOTROM_SUPPORTED)
+          void'(rvviRefMemorySetPrivilege(`BOOTROM_BASE, (`BOOTROM_BASE + `BOOTROM_RANGE), PRIV_X));
+      if (`UNCORE_RAM_SUPPORTED)
+          void'(rvviRefMemorySetPrivilege(`UNCORE_RAM_BASE, (`UNCORE_RAM_BASE + `UNCORE_RAM_RANGE), PRIV_RWX));
+      if (`EXT_MEM_SUPPORTED)
+          void'(rvviRefMemorySetPrivilege(`EXT_MEM_BASE, (`EXT_MEM_BASE + `EXT_MEM_RANGE), PRIV_RWX));
+          
+      if (`CLINT_SUPPORTED) begin
+          void'(rvviRefMemorySetPrivilege(`CLINT_BASE, (`CLINT_BASE + `CLINT_RANGE), PRIV_RW));
+          void'(rvviRefMemorySetVolatile(`CLINT_BASE, (`CLINT_BASE + `CLINT_RANGE)));
+      end
+      if (`GPIO_SUPPORTED) begin
+          void'(rvviRefMemorySetPrivilege(`GPIO_BASE, (`GPIO_BASE + `GPIO_RANGE), PRIV_RW));
+          void'(rvviRefMemorySetVolatile(`GPIO_BASE, (`GPIO_BASE + `GPIO_RANGE)));
+      end
+      if (`UART_SUPPORTED) begin
+          void'(rvviRefMemorySetVolatile(`CLINT_BASE, (`CLINT_BASE + `CLINT_RANGE)));
+          void'(rvviRefMemorySetPrivilege(`CLINT_BASE, (`CLINT_BASE + `CLINT_RANGE), PRIV_RW));
+      end
+      if (`PLIC_SUPPORTED) begin
+          void'(rvviRefMemorySetPrivilege(`PLIC_BASE, (`PLIC_BASE + `PLIC_RANGE), PRIV_RW));
+          void'(rvviRefMemorySetVolatile(`PLIC_BASE, (`PLIC_BASE + `PLIC_RANGE)));
+      end
+      if (`SDC_SUPPORTED) begin
+          void'(rvviRefMemorySetPrivilege(`SDC_BASE, (`SDC_BASE + `SDC_RANGE), PRIV_RW));
+          void'(rvviRefMemorySetVolatile(`SDC_BASE, (`SDC_BASE + `SDC_RANGE)));
+      end
 
       if(`XLEN==32) begin
           void'(rvviRefCsrSetVolatile(0, 32'hC80));   // CYCLEH
@@ -166,14 +206,15 @@ module testbench;
           void'(rvviRefCsrSetVolatile(0, 32'hB82));   // MINSTRETH
       end
 
-      // Enable the trace2log module
-      if ($value$plusargs("TRACE2LOG_ENABLE=%d", TRACE2LOG_ENABLE)) begin
-        msgnote($sformatf("%m @ t=%0t: TRACE2LOG_ENABLE is %0d", $time, TRACE2LOG_ENABLE));
-      end
-      
-      if ($value$plusargs("TRACE2COV_ENABLE=%d", TRACE2COV_ENABLE)) begin
-        msgnote($sformatf("%m @ t=%0t: TRACE2COV_ENABLE is %0d", $time, TRACE2COV_ENABLE));
-      end
+      // These should be done in the attached client
+//      // Enable the trace2log module
+//      if ($value$plusargs("TRACE2LOG_ENABLE=%d", TRACE2LOG_ENABLE)) begin
+//        msgnote($sformatf("%m @ t=%0t: TRACE2LOG_ENABLE is %0d", $time, TRACE2LOG_ENABLE));
+//      end
+//      
+//      if ($value$plusargs("TRACE2COV_ENABLE=%d", TRACE2COV_ENABLE)) begin
+//        msgnote($sformatf("%m @ t=%0t: TRACE2COV_ENABLE is %0d", $time, TRACE2COV_ENABLE));
+//      end
     end
 
     final begin