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https://github.com/openhwgroup/cvw
synced 2025-02-03 02:05:21 +00:00
correct c.sext.b encoding and remove unreachable code in 01100 case
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@ -165,14 +165,14 @@ module decompress import cvw::*; #(parameter cvw_t P) (
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InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
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else // if (instr16[6:5] == 2'b11)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
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else if (instr16[12:10] == 3'b111) begin
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else begin // (instr16[12:10] == 3'b111)
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if (instr16[6:5] == 2'b00 & P.XLEN > 32)
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InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
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else if (instr16[6:5] == 2'b01 & P.XLEN > 32)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
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else if (instr16[6:2] == 5'b11000 & P.ZCB_SUPPORTED)
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InstrD = {12'b000011111111, rds1p, 3'b111, rds1p, 7'b0010011}; // c.zext.b = andi rd, rs1, 255
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else if (instr16[6:2] == 5'b10101 & P.ZCB_SUPPORTED)
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else if (instr16[6:2] == 5'b11001 & P.ZCB_SUPPORTED)
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InstrD = {12'b011000000100, rds1p, 3'b001, rds1p, 7'b0010011}; // c.sext.b
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else if (instr16[6:2] == 5'b11010 & P.ZCB_SUPPORTED)
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InstrD = {7'b0000100, 5'b00000, rds1p, 3'b100, rds1p, 3'b011, P.XLEN > 32, 3'b011}; // c.zext.h
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@ -188,9 +188,9 @@ module decompress import cvw::*; #(parameter cvw_t P) (
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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end else begin // illegal instruction
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/** end else begin // illegal instruction
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap **/
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end
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5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
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5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
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