Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

made performance counters count branch misprediction

Browse Source
This commit is contained in:
Shreya Sanghai 2021-03-16 11:24:17 -04:00
parent 74f1641c5a
commit 08e9149e20
3 changed files with 5 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
wally-pipelined/src/privileged/csr.sv
View File

@ -33,7 +33,7 @@ module csr (
input logic [`XLEN-1:0] PCM, SrcAM, input logic [`XLEN-1:0] PCM, SrcAM,
input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
input logic TimerIntM, ExtIntM, SwIntM, input logic TimerIntM, ExtIntM, SwIntM,
input logic InstrValidW, FloatRegWriteW, LoadStallD, input logic InstrValidW, FloatRegWriteW, LoadStallD, BPPredWrongE,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic [`XLEN-1:0] CauseM, NextFaultMtvalM, input logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
output logic [1:0] STATUS_MPP, output logic [1:0] STATUS_MPP,

5
wally-pipelined/src/privileged/csrc.sv
View File

@ -29,7 +29,7 @@
module csrc ( module csrc (
input logic clk, reset, input logic clk, reset,
input logic InstrValidW, LoadStallD, CSRMWriteM, input logic InstrValidW, LoadStallD, CSRMWriteM, BPPredWrongE,
input logic [11:0] CSRAdrM, input logic [11:0] CSRAdrM,
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
input logic [`XLEN-1:0] CSRWriteValM, input logic [`XLEN-1:0] CSRWriteValM,
@ -62,7 +62,8 @@ module csrc (
assign MCOUNTEN[1] = 1'b0; assign MCOUNTEN[1] = 1'b0;
assign MCOUNTEN[2] = InstrValidW; assign MCOUNTEN[2] = InstrValidW;
assign MCOUNTEN[3] = LoadStallD; assign MCOUNTEN[3] = LoadStallD;
assign MCOUNTEN[`COUNTERS:4] = 0; assign MCOUNTEN[4] = BPPredWrongE;
assign MCOUNTEN[`COUNTERS:5] = 0;
genvar j; genvar j;
generate generate

2
wally-pipelined/src/privileged/privileged.sv
View File

@ -36,7 +36,7 @@ module privileged (
output logic [`XLEN-1:0] CSRReadValW, output logic [`XLEN-1:0] CSRReadValW,
output logic [`XLEN-1:0] PrivilegedNextPCM, output logic [`XLEN-1:0] PrivilegedNextPCM,
output logic RetM, TrapM, output logic RetM, TrapM,
input logic InstrValidW, FloatRegWriteW, LoadStallD, input logic InstrValidW, FloatRegWriteW, LoadStallD, BPPredWrongE,
input logic PrivilegedM, input logic PrivilegedM,
input logic InstrMisalignedFaultM, InstrAccessFaultF, IllegalIEUInstrFaultD, input logic InstrMisalignedFaultM, InstrAccessFaultF, IllegalIEUInstrFaultD,
input logic LoadMisalignedFaultM, LoadAccessFaultM, input logic LoadMisalignedFaultM, LoadAccessFaultM,