made performance counters count branch misprediction

wally-pipelined/src/privileged/csr.sv

@@ -33,7 +33,7 @@ module csr (
   input  logic [`XLEN-1:0] PCM, SrcAM,
   input  logic             CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
   input  logic             TimerIntM, ExtIntM, SwIntM,
-  input  logic             InstrValidW, FloatRegWriteW, LoadStallD,
+  input  logic             InstrValidW, FloatRegWriteW, LoadStallD, BPPredWrongE,
   input  logic [1:0]       NextPrivilegeModeM, PrivilegeModeW,
   input  logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
   output logic [1:0]       STATUS_MPP,

wally-pipelined/src/privileged/csrc.sv

@@ -29,7 +29,7 @@
 
 module csrc ( 
     input  logic             clk, reset,
-    input  logic             InstrValidW, LoadStallD, CSRMWriteM,
+    input  logic             InstrValidW, LoadStallD, CSRMWriteM, BPPredWrongE,
     input  logic [11:0]      CSRAdrM,
     input  logic [1:0]       PrivilegeModeW,
     input  logic [`XLEN-1:0] CSRWriteValM,
@@ -62,7 +62,8 @@ module csrc (
     assign MCOUNTEN[1] = 1'b0;
     assign MCOUNTEN[2] = InstrValidW;
     assign MCOUNTEN[3] = LoadStallD;
-    assign MCOUNTEN[`COUNTERS:4] = 0; 
+    assign MCOUNTEN[4] = BPPredWrongE;
+    assign MCOUNTEN[`COUNTERS:5] = 0; 
 
     genvar j;       
     generate

wally-pipelined/src/privileged/privileged.sv

@@ -36,7 +36,7 @@ module privileged (
   output logic [`XLEN-1:0] CSRReadValW,
   output logic [`XLEN-1:0] PrivilegedNextPCM,
   output logic             RetM, TrapM,
-  input  logic             InstrValidW, FloatRegWriteW, LoadStallD,
+  input  logic             InstrValidW, FloatRegWriteW, LoadStallD, BPPredWrongE,
   input  logic             PrivilegedM,
   input  logic             InstrMisalignedFaultM, InstrAccessFaultF, IllegalIEUInstrFaultD,
   input  logic             LoadMisalignedFaultM, LoadAccessFaultM,