From a766c2bb67acf943cd71d2f800380c598eefe3b3 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 31 Dec 2024 01:02:47 -0800 Subject: [PATCH 1/6] Update riscv-arch-test --- addins/riscv-arch-test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index a079bb263..8b6893e7b 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit a079bb263b04dde4028efee134f3a4e42799a5ca +Subproject commit 8b6893e7b363d310f1196146fe1f8316919e6338 From 89a3e3baa5726a1e8c3f8561c71d5ca924788b35 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 31 Dec 2024 02:16:37 -0800 Subject: [PATCH 2/6] Update VM sv32 test list --- testbench/tests.vh | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index bff553a1f..1c6746fd4 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -241,22 +241,30 @@ string arch64pmp[] = '{ string arch32vm_sv32[] = '{ `RISCVARCHTEST, + "rv32i_m/vm_sv32/src/mstatus_tvm_test.S", "rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S", "rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S", "rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S", "rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S", + "rv32i_m/vm_sv32/src/satp_access_tests.S", "rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S", "rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S", "rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S", "rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S", "rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S", "rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S", + "rv32i_m/vm_sv32/src/vm_mprv_S_mode.S", + "rv32i_m/vm_sv32/src/vm_mprv_U_mode.S", + "rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S", + "rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S", "rv32i_m/vm_sv32/src/vm_mxr_S_mode.S", "rv32i_m/vm_sv32/src/vm_mxr_U_mode.S", "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S", "rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S", - "rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S", - "rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S", + "rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S", "rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S", "rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S", "rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S", From 67843e647a966c520ed94ee1eb6afff23e561cec Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 31 Dec 2024 02:17:49 -0800 Subject: [PATCH 3/6] Mostly enable riscv-arch-test zcf and zcd tests Some tests disabled pending riscv-arch-test issue 590 --- testbench/testbench.sv | 10 ++++++++-- testbench/tests.vh | 26 ++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 4a40e1e87..a9ce97371 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -145,7 +145,9 @@ module testbench; "arch64i": tests = arch64i; "arch64priv": tests = arch64priv; "arch64c": if (P.ZCA_SUPPORTED) - if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; + if (P.ZICSR_SUPPORTED) + if (P.ZCD_SUPPORTED) tests = {arch64c, arch64cpriv, arch64zcd}; + else tests = {arch64c, arch64cpriv}; else tests = {arch64c}; "arch64m": if (P.M_SUPPORTED) tests = arch64m; "arch64a_amo": if (P.ZAAMO_SUPPORTED) tests = arch64a_amo; @@ -192,7 +194,11 @@ module testbench; "arch32i": tests = arch32i; "arch32priv": tests = arch32priv; "arch32c": if (P.C_SUPPORTED) - if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv}; + if (P.ZICSR_SUPPORTED) + if (P.ZCF_SUPPORTED) + if (P.ZCD_SUPPORTED) tests = {arch32c, arch32cpriv, arch32zcf, arch32zcd}; + else tests = {arch32c, arch32cpriv, arch32zcf}; + else tests = {arch32c, arch32cpriv}; else tests = {arch32c}; "arch32m": if (P.M_SUPPORTED) tests = arch32m; "arch32a_amo": if (P.ZAAMO_SUPPORTED) tests = arch32a_amo; diff --git a/testbench/tests.vh b/testbench/tests.vh index 1c6746fd4..fefc02aba 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -536,6 +536,15 @@ string arch64cpriv[] = '{ "rv64i_m/C/src/cebreak-01.S" }; +// Tests commented out pending riscv-arch-test issue #590 +string arch64zcd[] = '{ + // `RISCVARCHTEST, + "rv64i_m/D_Zcd/src/c.fld-01.S", + "rv64i_m/D_Zcd/src/c.fldsp-01.S", + "rv64i_m/D_Zcd/src/c.fsd-01.S", + "rv64i_m/D_Zcd/src/c.fsdsp-01.S" +}; + string arch64i[] = '{ `RISCVARCHTEST, "rv64i_m/I/src/add-01.S", @@ -3361,6 +3370,23 @@ string arch32cpriv[] = '{ "rv32i_m/C/src/cebreak-01.S" }; +// Tests commented out pending riscv-arch-test issue #590 +string arch32zcf[] = '{ + // `RISCVARCHTEST, + // "rv32i_m/F_Zcf/src/c.flw-01.S", + // "rv32i_m/F_Zcf/src/c.flwsp-01.S", + // "rv32i_m/F_Zcf/src/c.fsw-01.S", + "rv32i_m/F_Zcf/src/c.fswsp-01.S" +}; + +// Tests commented out pending riscv-arch-test issue #590 +string arch32zcd[] = '{ + // `RISCVARCHTEST, + "rv32i_m/D_Zcd/src/c.fld-01.S", + // "rv32i_m/D_Zcd/src/c.fldsp-01.S", + "rv32i_m/D_Zcd/src/c.fsd-01.S", + "rv32i_m/D_Zcd/src/c.fsdsp-01.S" +}; string arch32i[] = '{ `RISCVARCHTEST, From 8d2b1ff0578f2dacc3ebeac6d8e01cfd4a7956d6 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 31 Dec 2024 02:20:17 -0800 Subject: [PATCH 4/6] Update riscv-arch-test again --- addins/riscv-arch-test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 8b6893e7b..832ab11c0 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 8b6893e7b363d310f1196146fe1f8316919e6338 +Subproject commit 832ab11c093f332ef83ca9c0ef55845071a7cb3d From 5a14864ca99339433da5ce42cc1de8c9aea4e2a8 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 31 Dec 2024 02:46:16 -0800 Subject: [PATCH 5/6] Add new riscv-arch-test Zfh convert tests --- testbench/tests.vh | 54 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/testbench/tests.vh b/testbench/tests.vh index fefc02aba..a5704095e 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1017,10 +1017,37 @@ string arch64zfh[] = '{ "rv64i_m/Zfh/src/fadd_b7-01.S", "rv64i_m/Zfh/src/fadd_b8-01.S", "rv64i_m/Zfh/src/fclass_b1-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b1-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b22-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b23-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b24-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b27-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b28-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b29-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b1-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b22-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b23-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b24-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b27-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b28-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b29-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b1-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b22-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b23-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b24-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b27-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b28-01.S", + "rv64i_m/Zfh/src/fcvt.h.s_b29-01.S", "rv64i_m/Zfh/src/fcvt.h.w_b25-01.S", "rv64i_m/Zfh/src/fcvt.h.w_b26-01.S", "rv64i_m/Zfh/src/fcvt.h.wu_b25-01.S", "rv64i_m/Zfh/src/fcvt.h.wu_b26-01.S", + "rv64i_m/Zfh/src/fcvt.s.h_b22-01.S", + "rv64i_m/Zfh/src/fcvt.s.h_b23-01.S", + "rv64i_m/Zfh/src/fcvt.s.h_b24-01.S", + "rv64i_m/Zfh/src/fcvt.s.h_b27-01.S", + "rv64i_m/Zfh/src/fcvt.s.h_b28-01.S", + "rv64i_m/Zfh/src/fcvt.s.h_b29-01.S", "rv64i_m/Zfh/src/fcvt.w.h_b1-01.S", "rv64i_m/Zfh/src/fcvt.w.h_b22-01.S", "rv64i_m/Zfh/src/fcvt.w.h_b23-01.S", @@ -2430,10 +2457,37 @@ string arch32zfh[] = '{ "rv32i_m/Zfh/src/fadd_b7-01.S", "rv32i_m/Zfh/src/fadd_b8-01.S", "rv32i_m/Zfh/src/fclass_b1-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b1-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b22-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b23-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b24-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b27-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b28-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b29-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b1-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b22-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b23-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b24-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b27-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b28-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b29-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b1-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b22-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b23-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b24-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b27-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b28-01.S", + "rv32i_m/Zfh/src/fcvt.h.s_b29-01.S", "rv32i_m/Zfh/src/fcvt.h.w_b25-01.S", "rv32i_m/Zfh/src/fcvt.h.w_b26-01.S", "rv32i_m/Zfh/src/fcvt.h.wu_b25-01.S", "rv32i_m/Zfh/src/fcvt.h.wu_b26-01.S", + "rv32i_m/Zfh/src/fcvt.s.h_b22-01.S", + "rv32i_m/Zfh/src/fcvt.s.h_b23-01.S", + "rv32i_m/Zfh/src/fcvt.s.h_b24-01.S", + "rv32i_m/Zfh/src/fcvt.s.h_b27-01.S", + "rv32i_m/Zfh/src/fcvt.s.h_b28-01.S", + "rv32i_m/Zfh/src/fcvt.s.h_b29-01.S", "rv32i_m/Zfh/src/fcvt.w.h_b1-01.S", "rv32i_m/Zfh/src/fcvt.w.h_b22-01.S", "rv32i_m/Zfh/src/fcvt.w.h_b23-01.S", From 7e021f93321d5f0fa98f8328db5a3d713c416132 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Tue, 31 Dec 2024 11:01:07 -0800 Subject: [PATCH 6/6] Only add Zfh to D conversion tests if D supported --- testbench/testbench.sv | 8 ++++-- testbench/tests.vh | 64 +++++++++++++++++++++++------------------- 2 files changed, 41 insertions(+), 31 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index a9ce97371..8ba10b292 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -174,7 +174,9 @@ module testbench; "arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs; "arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz; "arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb; - "arch64zfh": if (P.ZFH_SUPPORTED) tests = arch64zfh; + "arch64zfh": if (P.ZFH_SUPPORTED) + if (P.D_SUPPORTED) tests = {arch64zfh, arch64zfh_d}; + else tests = arch64zfh; "arch64zfh_fma": if (P.ZFH_SUPPORTED) tests = arch64zfh_fma; "arch64zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch64zfh_divsqrt; "arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf; @@ -222,7 +224,9 @@ module testbench; "arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs; "arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz; "arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb; - "arch32zfh": if (P.ZFH_SUPPORTED) tests = arch32zfh; + "arch32zfh": if (P.ZFH_SUPPORTED) + if (P.D_SUPPORTED) tests = {arch32zfh, arch32zfh_d}; + else tests = arch32zfh; "arch32zfh_fma": if (P.ZFH_SUPPORTED) tests = arch32zfh_fma; "arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt; "arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf; diff --git a/testbench/tests.vh b/testbench/tests.vh index a5704095e..817b8d6d5 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1017,20 +1017,6 @@ string arch64zfh[] = '{ "rv64i_m/Zfh/src/fadd_b7-01.S", "rv64i_m/Zfh/src/fadd_b8-01.S", "rv64i_m/Zfh/src/fclass_b1-01.S", - "rv64i_m/Zfh/src/fcvt.d.h_b1-01.S", - "rv64i_m/Zfh/src/fcvt.d.h_b22-01.S", - "rv64i_m/Zfh/src/fcvt.d.h_b23-01.S", - "rv64i_m/Zfh/src/fcvt.d.h_b24-01.S", - "rv64i_m/Zfh/src/fcvt.d.h_b27-01.S", - "rv64i_m/Zfh/src/fcvt.d.h_b28-01.S", - "rv64i_m/Zfh/src/fcvt.d.h_b29-01.S", - "rv64i_m/Zfh/src/fcvt.h.d_b1-01.S", - "rv64i_m/Zfh/src/fcvt.h.d_b22-01.S", - "rv64i_m/Zfh/src/fcvt.h.d_b23-01.S", - "rv64i_m/Zfh/src/fcvt.h.d_b24-01.S", - "rv64i_m/Zfh/src/fcvt.h.d_b27-01.S", - "rv64i_m/Zfh/src/fcvt.h.d_b28-01.S", - "rv64i_m/Zfh/src/fcvt.h.d_b29-01.S", "rv64i_m/Zfh/src/fcvt.h.s_b1-01.S", "rv64i_m/Zfh/src/fcvt.h.s_b22-01.S", "rv64i_m/Zfh/src/fcvt.h.s_b23-01.S", @@ -1174,7 +1160,23 @@ string arch64zfh[] = '{ "rv64i_m/Zfh/src/fnmsub_b8-01.S" }; - +string arch64zfh_d[] = '{ + // `RISCVARCHTEST, + "rv64i_m/Zfh/src/fcvt.d.h_b1-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b22-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b23-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b24-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b27-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b28-01.S", + "rv64i_m/Zfh/src/fcvt.d.h_b29-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b1-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b22-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b23-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b24-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b27-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b28-01.S", + "rv64i_m/Zfh/src/fcvt.h.d_b29-01.S" +}; string arch64d_fma[] = '{ `RISCVARCHTEST, @@ -2457,20 +2459,6 @@ string arch32zfh[] = '{ "rv32i_m/Zfh/src/fadd_b7-01.S", "rv32i_m/Zfh/src/fadd_b8-01.S", "rv32i_m/Zfh/src/fclass_b1-01.S", - "rv32i_m/Zfh/src/fcvt.d.h_b1-01.S", - "rv32i_m/Zfh/src/fcvt.d.h_b22-01.S", - "rv32i_m/Zfh/src/fcvt.d.h_b23-01.S", - "rv32i_m/Zfh/src/fcvt.d.h_b24-01.S", - "rv32i_m/Zfh/src/fcvt.d.h_b27-01.S", - "rv32i_m/Zfh/src/fcvt.d.h_b28-01.S", - "rv32i_m/Zfh/src/fcvt.d.h_b29-01.S", - "rv32i_m/Zfh/src/fcvt.h.d_b1-01.S", - "rv32i_m/Zfh/src/fcvt.h.d_b22-01.S", - "rv32i_m/Zfh/src/fcvt.h.d_b23-01.S", - "rv32i_m/Zfh/src/fcvt.h.d_b24-01.S", - "rv32i_m/Zfh/src/fcvt.h.d_b27-01.S", - "rv32i_m/Zfh/src/fcvt.h.d_b28-01.S", - "rv32i_m/Zfh/src/fcvt.h.d_b29-01.S", "rv32i_m/Zfh/src/fcvt.h.s_b1-01.S", "rv32i_m/Zfh/src/fcvt.h.s_b22-01.S", "rv32i_m/Zfh/src/fcvt.h.s_b23-01.S", @@ -2596,6 +2584,24 @@ string arch32zfh[] = '{ "rv32i_m/Zfh/src/fnmsub_b8-01.S" }; +string arch32zfh_d[] = '{ + // `RISCVARCHTEST, + "rv32i_m/Zfh/src/fcvt.d.h_b1-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b22-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b23-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b24-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b27-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b28-01.S", + "rv32i_m/Zfh/src/fcvt.d.h_b29-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b1-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b22-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b23-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b24-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b27-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b28-01.S", + "rv32i_m/Zfh/src/fcvt.h.d_b29-01.S" +}; + string arch32zfaf[] = '{ `RISCVARCHTEST, "rv32i_m/F_Zfa/src/fround_b1-01.S",