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update removal of underscores from aes_instructions

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This commit is contained in:
James E. Stine 2024-03-09 13:28:47 -06:00
parent 8821386fe5
commit 08c7ddd61d
11 changed files with 108 additions and 110 deletions
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22
src/ieu/aes_instructions/aes32dsi.sv
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@ -28,32 +28,32 @@
module aes32dsi(input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] Data_Out);
output logic [31:0] DataOut);
// Declare Intermediary logic
logic [4:0] shamt;
logic [31:0] Sbox_In_32;
logic [7:0] Sbox_In;
logic [7:0] Sbox_Out;
logic [31:0] SboxIn32;
logic [7:0] SboxIn;
logic [7:0] SboxOut;
logic [31:0] so;
logic [31:0] so_rotate;
logic [31:0] sorotate;
// shamt = bs * 8
assign shamt = {bs, 3'b0};
// Shift rs2 right by shamt and take the lower byte
assign Sbox_In_32 = (rs2 >> shamt);
assign Sbox_In = Sbox_In_32[7:0];
assign SboxIn32 = (rs2 >> shamt);
assign SboxIn = SboxIn32[7:0];
// Apply inverse sbox to si
aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out));
aesinvsbox inv_sbox(.in(SboxIn), .out(SboxOut));
// Pad output of inverse substitution box
assign so = {24'h0, Sbox_Out};
assign so = {24'h0, SboxOut};
// Rotate the substitution box output left by shamt (bs * 8)
assign so_rotate = (so << shamt) | (so >> (32 - shamt));
assign sorotate = (so << shamt) | (so >> (32 - shamt));
// Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));"
assign Data_Out = rs1 ^ so_rotate;
assign DataOut = rs1 ^ sorotate;
endmodule

24
src/ieu/aes_instructions/aes32dsmi.sv
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@ -28,36 +28,36 @@
module aes32dsmi(input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] Data_Out);
output logic [31:0] DataOut);
// Declare Intermediary logic
logic [4:0] shamt;
logic [31:0] Sbox_In_32;
logic [7:0] Sbox_In;
logic [7:0] Sbox_Out;
logic [31:0] SboxIn32;
logic [7:0] SboxIn;
logic [7:0] SboxOut;
logic [31:0] so;
logic [31:0] mixed;
logic [31:0] mixed_rotate;
logic [31:0] mixedrotate;
// shamt = bs * 8
assign shamt = {bs, 3'b0};
// Shift rs2 right by shamt and take the lower byte
assign Sbox_In_32 = (rs2 >> shamt);
assign Sbox_In = Sbox_In_32[7:0];
assign SboxIn32 = (rs2 >> shamt);
assign SboxIn = SboxIn32[7:0];
// Apply inverse sbox to si
aes_inv_sbox inv_sbox(.in(Sbox_In), .out(Sbox_Out));
aesinvsbox inv_sbox(.in(SboxIn), .out(SboxOut));
// Pad output of inverse substitution box
assign so = {24'h0, Sbox_Out};
assign so = {24'h0, SboxOut};
// Run so through the mixword AES function
aes_inv_mixcolumns mix(.in(so), .out(mixed));
aesinvmixcolumns mix(.in(so), .out(mixed));
// Rotate the substitution box output left by shamt (bs * 8)
assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt));
assign mixedrotate = (mixed << shamt) | (mixed >> (32 - shamt));
// Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));"
assign Data_Out = rs1 ^ mixed_rotate;
assign DataOut = rs1 ^ mixedrotate;
endmodule

22
src/ieu/aes_instructions/aes32esi.sv
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@ -28,34 +28,34 @@
module aes32esi(input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] Data_Out);
output logic [31:0] DataOut);
// Declare Intermediary logic
logic [4:0] shamt;
logic [31:0] Sbox_In_32;
logic [7:0] Sbox_In;
logic [7:0] Sbox_Out;
logic [31:0] SboxIn32;
logic [7:0] SboxIn;
logic [7:0] SboxOut;
logic [31:0] so;
logic [31:0] so_rotate;
logic [31:0] sorotate;
// Shift bs by 3 to get shamt
assign shamt = {bs, 3'b0};
// Shift rs2 right by shamt to get sbox input
assign Sbox_In_32 = (rs2 >> shamt);
assign SboxIn32 = (rs2 >> shamt);
// Take the bottom byte as an input to the substitution box
assign Sbox_In = Sbox_In_32[7:0];
assign SboxIn = SboxIn32[7:0];
// Substitute
aes_sbox subbox(.in(Sbox_In), .out(Sbox_Out));
aessbox subbox(.in(SboxIn), .out(SboxOut));
// Pad sbox output
assign so = {24'h0, Sbox_Out};
assign so = {24'h0, SboxOut};
// Rotate so left by shamt
assign so_rotate = (so << shamt) | (so >> (32 - shamt));
assign sorotate = (so << shamt) | (so >> (32 - shamt));
// Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt));
assign Data_Out = rs1 ^ so_rotate;
assign DataOut = rs1 ^ sorotate;
endmodule

26
src/ieu/aes_instructions/aes32esmi.sv
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@ -28,38 +28,38 @@
module aes32esmi(input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] Data_Out);
output logic [31:0] DataOut);
// Declare Intermediary logic
logic [4:0] shamt;
logic [31:0] Sbox_In_32;
logic [7:0] Sbox_In;
logic [7:0] Sbox_Out;
logic [31:0] SboxIn32;
logic [7:0] SboxIn;
logic [7:0] SboxOut;
logic [31:0] so;
logic [31:0] mixed;
logic [31:0] mixed_rotate;
logic [31:0] mixedrotate;
// Shift bs by 3 to get shamt
assign shamt = {bs, 3'b0};
// Shift rs2 right by shamt to get sbox input
assign Sbox_In_32 = (rs2 >> shamt);
assign SboxIn32 = (rs2 >> shamt);
// Take the bottom byte as an input to the substitution box
assign Sbox_In = Sbox_In_32[7:0];
assign SboxIn = SboxIn32[7:0];
// Substitute
aes_sbox sbox(.in(Sbox_In), .out(Sbox_Out));
aessbox sbox(.in(SboxIn), .out(SboxOut));
// Pad sbox output
assign so = {24'h0, Sbox_Out};
assign so = {24'h0, SboxOut};
// Mix Word using aes_mixword component
aes_mixcolumns mwd(.in(so), .out(mixed));
// Mix Word using aesmixword component
aesmixcolumns mwd(.in(so), .out(mixed));
// Rotate so left by shamt
assign mixed_rotate = (mixed << shamt) | (mixed >> (32 - shamt));
assign mixedrotate = (mixed << shamt) | (mixed >> (32 - shamt));
// Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt));
assign Data_Out = rs1 ^ mixed_rotate;
assign DataOut = rs1 ^ mixedrotate;
endmodule

16
src/ieu/aes_instructions/aes64ds.sv
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@ -27,20 +27,20 @@
module aes64ds(input logic [63:0] rs1,
input logic [63:0] rs2,
output logic [63:0] Data_Out);
output logic [63:0] DataOut);
// Intermediary Logic
logic [127:0] ShiftRow_Out;
logic [31:0] Sbox_Out_0;
logic [31:0] Sbox_Out_1;
logic [127:0] ShiftRowOut;
logic [31:0] SboxOut0;
logic [31:0] SboxOut1;
// Apply inverse shiftrows to rs2 and rs1
aes_inv_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out));
aesinvshiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRowOut));
// Apply full word inverse substitution to lower 2 words of shiftrow out
aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0));
aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1));
aesinvsboxword inv_sbox_0(.in(ShiftRowOut[31:0]), .out(SboxOut0));
aesinvsboxword inv_sbox_1(.in(ShiftRowOut[63:32]), .out(SboxOut1));
// Concatenate the two substitution outputs to get result
assign Data_Out = {Sbox_Out_1, Sbox_Out_0};
assign DataOut = {SboxOut1, SboxOut0};
endmodule

24
src/ieu/aes_instructions/aes64dsm.sv
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@ -27,26 +27,26 @@
module aes64dsm(input logic [63:0] rs1,
input logic [63:0] rs2,
output logic [63:0] Data_Out);
output logic [63:0] DataOut);
// Intermediary Logic
logic [127:0] ShiftRow_Out;
logic [31:0] Sbox_Out_0;
logic [31:0] Sbox_Out_1;
logic [31:0] Mixcol_Out_0;
logic [31:0] Mixcol_Out_1;
logic [127:0] ShiftRowOut;
logic [31:0] SboxOut0;
logic [31:0] SboxOut1;
logic [31:0] MixcolOut0;
logic [31:0] MixcolOut1;
// Apply inverse shiftrows to rs2 and rs1
aes_inv_shiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRow_Out));
aesinvshiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRowOut));
// Apply full word inverse substitution to lower 2 words of shiftrow out
aes_inv_sbox_word inv_sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out_0));
aes_inv_sbox_word inv_sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out_1));
aesinvsboxword invsbox0(.in(ShiftRowOut[31:0]), .out(SboxOut0));
aesinvsboxword invsbox1(.in(ShiftRowOut[63:32]), .out(SboxOut1));
// Apply inverse mixword to sbox outputs
aes_inv_mixcolumns inv_mw_0(.in(Sbox_Out_0), .out(Mixcol_Out_0));
aes_inv_mixcolumns inv_mw_1(.in(Sbox_Out_1), .out(Mixcol_Out_1));
aesinvmixcolumns invmw0(.in(SboxOut0), .out(MixcolOut0));
aesinvmixcolumns invmw1(.in(SboxOut1), .out(MixcolOut1));
// Concatenate mixed words for output
assign Data_Out = {Mixcol_Out_1, Mixcol_Out_0};
assign DataOut = {MixcolOut1, MixcolOut0};
endmodule

10
src/ieu/aes_instructions/aes64es.sv
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@ -27,15 +27,15 @@
module aes64es(input logic [63:0] rs1,
input logic [63:0] rs2,
output logic [63:0] Data_Out);
output logic [63:0] DataOut);
// Intermediary Signals
logic [127:0] ShiftRow_Out;
logic [127:0] ShiftRowOut;
// AES shiftrow unit
aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out));
aesshiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRowOut));
// Apply substitution box to 2 lower words
aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Data_Out[31:0]));
aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Data_Out[63:32]));
aessboxword sbox0(.in(ShiftRowOut[31:0]), .out(DataOut[31:0]));
aessboxword sbox1(.in(ShiftRowOut[63:32]), .out(DataOut[63:32]));
endmodule

16
src/ieu/aes_instructions/aes64esm.sv
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@ -27,20 +27,20 @@
module aes64esm(input logic [63:0] rs1,
input logic [63:0] rs2,
output logic [63:0] Data_Out);
output logic [63:0] DataOut);
// Intermediary Signals
logic [127:0] ShiftRow_Out;
logic [63:0] Sbox_Out;
logic [127:0] ShiftRowOut;
logic [63:0] SboxOut;
// AES shiftrow unit
aes_shiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRow_Out));
aesshiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRowOut));
// Apply substitution box to 2 lower words
aes_sbox_word sbox_0(.in(ShiftRow_Out[31:0]), .out(Sbox_Out[31:0]));
aes_sbox_word sbox_1(.in(ShiftRow_Out[63:32]), .out(Sbox_Out[63:32]));
aessboxword sbox0(.in(ShiftRowOut[31:0]), .out(SboxOut[31:0]));
aessboxword sbox1(.in(ShiftRowOut[63:32]), .out(SboxOut[63:32]));
// Apply mix columns operations
aes_mixcolumns mw0(.in(Sbox_Out[31:0]), .out(Data_Out[31:0]));
aes_mixcolumns mw1(.in(Sbox_Out[63:32]), .out(Data_Out[63:32]));
aesmixcolumns mw0(.in(SboxOut[31:0]), .out(DataOut[31:0]));
aesmixcolumns mw1(.in(SboxOut[63:32]), .out(DataOut[63:32]));
endmodule

6
src/ieu/aes_instructions/aes64im.sv
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@ -26,8 +26,8 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module aes64im(input logic [63:0] rs1,
output logic [63:0] Data_Out);
output logic [63:0] DataOut);
aes_inv_mixcolumns inv_mw_0(.in(rs1[31:0]), .out(Data_Out[31:0]));
aes_inv_mixcolumns inv_mw_1(.in(rs1[63:32]), .out(Data_Out[63:32]));
aesinvmixcolumns inv_mw_0(.in(rs1[31:0]), .out(DataOut[31:0]));
aesinvmixcolumns inv_mw_1(.in(rs1[63:32]), .out(DataOut[63:32]));
endmodule

22
src/ieu/aes_instructions/aes64ks1i.sv
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@ -30,33 +30,31 @@ module aes64ks1i(input logic [3:0] roundnum,
output logic [63:0] rd);
// Instantiate intermediary logic signals
logic [7:0] rcon_preshift;
logic [7:0] rconPreShift;
logic [31:0] rcon;
logic lastRoundFlag;
logic [31:0] rs1_rotate;
logic [31:0] rs1Rotate;
logic [31:0] tmp2;
logic [31:0] Sbox_Out;
logic [31:0] SboxOut;
// Get rcon value from table
rcon_lut_128 rc(.RD(roundnum), .rcon_out(rcon_preshift));
rconlut128 rc(.RD(roundnum), .rconOut(rconPreShift));
// Shift RCON value
assign rcon = {24'b0, rcon_preshift};
assign rcon = {24'b0, rconPreShift};
// Flag will be set if roundnum = 0xA = 0b1010
assign lastRoundFlag = roundnum[3] & ~roundnum[2] & roundnum[1] & ~roundnum[0];
// Get rotated value fo ruse in tmp2
assign rs1_rotate = {rs1[39:32], rs1[63:40]};
assign rs1Rotate = {rs1[39:32], rs1[63:40]};
// Assign tmp2 to a mux based on lastRoundFlag
assign tmp2 = lastRoundFlag ? rs1[63:32] : rs1_rotate;
assign tmp2 = lastRoundFlag ? rs1[63:32] : rs1Rotate;
// Substitute bytes of value obtained for tmp2 using Rijndael sbox
aes_sbox_word sbox(.in(tmp2),.out(Sbox_Out));
assign rd[31:0] = Sbox_Out ^ rcon;
assign rd[63:32] = Sbox_Out ^ rcon;
aessboxword sbox(.in(tmp2),.out(SboxOut));
assign rd[31:0] = SboxOut ^ rcon;
assign rd[63:32] = SboxOut ^ rcon;
endmodule

30
src/ieu/aes_instructions/rcon_lut_128.sv → src/ieu/aes_instructions/rconlut128.sv
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@ -1,5 +1,5 @@
///////////////////////////////////////////
// rcon_lut_128.sv
// rconlut128.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
@ -25,24 +25,24 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module rcon_lut_128(input logic [3:0] RD,
output logic [7:0] rcon_out);
module rconlut128(input logic [3:0] RD,
output logic [7:0] rconOut);
always_comb
begin
case(RD)
4'h0 : rcon_out = 8'h01;
4'h1 : rcon_out = 8'h02;
4'h2 : rcon_out = 8'h04;
4'h3 : rcon_out = 8'h08;
4'h4 : rcon_out = 8'h10;
4'h5 : rcon_out = 8'h20;
4'h6 : rcon_out = 8'h40;
4'h7 : rcon_out = 8'h80;
4'h8 : rcon_out = 8'h1b;
4'h9 : rcon_out = 8'h36;
4'hA : rcon_out = 8'h00;
default : rcon_out = 8'h00;
4'h0 : rconOut = 8'h01;
4'h1 : rconOut = 8'h02;
4'h2 : rconOut = 8'h04;
4'h3 : rconOut = 8'h08;
4'h4 : rconOut = 8'h10;
4'h5 : rconOut = 8'h20;
4'h6 : rconOut = 8'h40;
4'h7 : rconOut = 8'h80;
4'h8 : rconOut = 8'h1b;
4'h9 : rconOut = 8'h36;
4'hA : rconOut = 8'h00;
default : rconOut = 8'h00;
endcase
end
endmodule