diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv index 786fa07d5..3d8383ce0 100755 --- a/pipelined/src/fpu/fcmp.sv +++ b/pipelined/src/fpu/fcmp.sv @@ -52,7 +52,7 @@ module fcmp ( 3'b010: CmpNVE = EitherSNaN;//equal 3'b001: CmpNVE = EitherNaN;//less than 3'b011: CmpNVE = EitherNaN;//less than or equal - default: CmpNVE = 1'b0; + default: CmpNVE = 1'bx; endcase end @@ -91,7 +91,7 @@ module fcmp ( `FMT2: if(`IEEE754) NaNRes = {{`FLEN-`LEN2{1'b1}}, XSgnE, {`NE2{1'b1}}, 1'b1, XManE[`NF-2:`NF-`NF2]}; else NaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; - default: NaNRes = (`FLEN)'(0); + default: NaNRes = {`FLEN{1'bx}}; endcase else if (`FPSIZES == 4) diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index fb0a2b81e..b7f6b2e60 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -24,18 +24,18 @@ module fctrl ( // FPU Instruction Decoder always_comb if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled - ControlsD = `FCTRLW'b0_0_00_00_000_0_1; + ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; else case(OpD) // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr 7'b0000111: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b1_0_10_00_000_0_0; // flw - 3'b011: ControlsD = `FCTRLW'b1_0_10_00_000_0_0; // fld - default: ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction + 3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0; // flw + 3'b011: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0; // fld + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase 7'b0100111: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b0_0_00_00_000_0_0; // fsw - 3'b011: ControlsD = `FCTRLW'b0_0_00_00_000_0_0; // fsd - default: ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction + 3'b010: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_0; // fsw + 3'b011: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_0; // fsd + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase 7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0; // fmadd 7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0; // fmsub @@ -45,29 +45,29 @@ module fctrl ( 7'b00000??: ControlsD = `FCTRLW'b1_0_01_10_110_0_0; // fadd 7'b00001??: ControlsD = `FCTRLW'b1_0_01_10_111_0_0; // fsub 7'b00010??: ControlsD = `FCTRLW'b1_0_01_10_100_0_0; // fmul - 7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_000_1_0; // fdiv - 7'b01011??: ControlsD = `FCTRLW'b1_0_01_01_001_1_0; // fsqrt + 7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0; // fdiv + 7'b01011??: ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0; // fsqrt 7'b00100??: case(Funct3D) - 3'b000: ControlsD = `FCTRLW'b1_0_00_00_000_0_0; // fsgnj - 3'b001: ControlsD = `FCTRLW'b1_0_00_00_001_0_0; // fsgnjn - 3'b010: ControlsD = `FCTRLW'b1_0_00_00_010_0_0; // fsgnjx - default: ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction + 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0; // fsgnj + 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0; // fsgnjn + 3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0; // fsgnjx + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase 7'b00101??: case(Funct3D) - 3'b000: ControlsD = `FCTRLW'b1_0_00_00_110_0_0; // fmin - 3'b001: ControlsD = `FCTRLW'b1_0_00_00_101_0_0; // fmax - default: ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction + 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0; // fmin + 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0; // fmax + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase 7'b10100??: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b0_1_00_00_010_0_0; // feq - 3'b001: ControlsD = `FCTRLW'b0_1_00_00_001_0_0; // flt - 3'b000: ControlsD = `FCTRLW'b0_1_00_00_011_0_0; // fle - default: ControlsD = `FCTRLW'b0_0_00_00_000__0_1; // non-implemented instruction + 3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0; // feq + 3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0; // flt + 3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0; // fle + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx__0_1; // non-implemented instruction endcase - 7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_10_00_000_0_0; // fclass - else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_00_000_0_0; // fmv.x.w to int reg - else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_00_000_0_0; // fmv.x.d to int reg - else ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction + 7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_10_xx_000_0_0; // fclass + else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0; // fmv.x.w to int reg + else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0; // fmv.x.d to int reg + else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction 7'b1101000: case(Rs2D[1:0]) 2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0; // fcvt.s.w w->s 2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0; // fcvt.s.wu wu->s @@ -80,7 +80,7 @@ module fctrl ( 2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0; // fcvt.l.s s->l 2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0; // fcvt.lu.s s->lu endcase - 7'b1111000: ControlsD = `FCTRLW'b1_0_00_00_011_0_0; // fmv.w.x to fp reg + 7'b1111000: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0; // fmv.w.x to fp reg 7'b0100000: ControlsD = `FCTRLW'b1_0_01_00_000_0_0; // fcvt.s.d 7'b1101001: case(Rs2D[1:0]) 2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0; // fcvt.d.w w->d @@ -94,11 +94,11 @@ module fctrl ( 2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0; // fcvt.l.d d->l 2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0; // fcvt.lu.d d->lu endcase - 7'b1111001: ControlsD = `FCTRLW'b1_0_00_00_011_0_0; // fmv.d.x to fp reg + 7'b1111001: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0; // fmv.d.x to fp reg 7'b0100001: ControlsD = `FCTRLW'b1_0_01_00_001_0_0; // fcvt.d.s - default: ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase - default: ControlsD = `FCTRLW'b0_0_00_00_000_0_1; // non-implemented instruction + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase // unswizzle control bits diff --git a/pipelined/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv index 4bc2242a0..a76122804 100644 --- a/pipelined/src/fpu/fcvt.sv +++ b/pipelined/src/fpu/fcvt.sv @@ -133,7 +133,7 @@ module fcvt ( `FMT: NewBiasToFp = (`NE-1)'(`BIAS); `FMT1: NewBiasToFp = (`NE-1)'(`BIAS1); `FMT2: NewBiasToFp = (`NE-1)'(`BIAS2); - default: NewBiasToFp = 1'bx; + default: NewBiasToFp = {`NE-1{1'bx}}; endcase assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp; diff --git a/pipelined/src/fpu/flags.sv b/pipelined/src/fpu/flags.sv index 334bc7336..09cae561e 100644 --- a/pipelined/src/fpu/flags.sv +++ b/pipelined/src/fpu/flags.sv @@ -34,7 +34,8 @@ module flags( logic FmaInvalid; // integer invalid flag logic DivInvalid; // integer invalid flag logic DivByZero; - logic [`NE-1:0] MaxExp; // the maximum exponent before overflow + logic ResExpGteMax; // is the result greater than or equal to the maximum floating point expoent + logic ShiftGtIntSz; // is the shift greater than the the integer size (use ResExp to account for possible roundning "shift") /////////////////////////////////////////////////////////////////////////////// // Flags @@ -43,56 +44,51 @@ module flags( if (`FPSIZES == 1) begin - assign MaxExp = ToInt&CvtOp ? Int64 ? (`NE)'(65) : (`NE)'(33) : {`NE{1'b1}}; + assign ResExpGteMax = &FullResExp[`NE-1:0] | FullResExp[`NE]; + assign ShiftGtIntSz = (|FullResExp[`NE:7]|(FullResExp[6]&~Int64)) | ((|FullResExp[4:0]|(FullResExp[5]&Int64))&((FullResExp[5]&~Int64) | FullResExp[6]&Int64)); end else if (`FPSIZES == 2) begin - assign MaxExp = ToInt&CvtOp ? Int64 ? (`NE)'($unsigned(65)) : (`NE)'($unsigned(33)) : - OutFmt ? {`NE{1'b1}} : {{`NE-`NE1{1'b0}}, {`NE1{1'b1}}}; + assign ResExpGteMax = OutFmt ? &FullResExp[`NE-1:0] | FullResExp[`NE] : &FullResExp[`NE1-1:0] | (|FullResExp[`NE:`NE1]); + assign ShiftGtIntSz = (|FullResExp[`NE:7]|(FullResExp[6]&~Int64)) | ((|FullResExp[4:0]|(FullResExp[5]&Int64))&((FullResExp[5]&~Int64) | FullResExp[6]&Int64)); end else if (`FPSIZES == 3) begin - logic [`NE-1:0] MaxExpFp; always_comb case (OutFmt) - `FMT: begin - MaxExpFp = {`NE{1'b1}}; - end - `FMT1: begin - MaxExpFp = {{`NE-`NE1{1'b0}}, {`NE1{1'b1}}}; - end - `FMT2: begin - MaxExpFp = {{`NE-`NE2{1'b0}}, {`NE2{1'b1}}}; - end - default: begin - MaxExpFp = 1'bx; - end + `FMT: ResExpGteMax = &FullResExp[`NE-1:0] | FullResExp[`NE]; + `FMT1: ResExpGteMax = &FullResExp[`NE1-1:0] | (|FullResExp[`NE:`NE1]); + `FMT2: ResExpGteMax = &FullResExp[`NE2-1:0] | (|FullResExp[`NE:`NE2]); + default: ResExpGteMax = 1'bx; endcase - assign MaxExp = ToInt&CvtOp ? Int64 ? (`NE)'(65) : (`NE)'(33) : MaxExpFp; + assign ShiftGtIntSz = (|FullResExp[`NE:7]|(FullResExp[6]&~Int64)) | ((|FullResExp[4:0]|(FullResExp[5]&Int64))&((FullResExp[5]&~Int64) | FullResExp[6]&Int64)); end else if (`FPSIZES == 4) begin - logic [`NE-1:0] MaxExpFp; always_comb case (OutFmt) - 2'h3: begin - MaxExpFp = {`Q_NE{1'b1}}; - end - 2'h1: begin - MaxExpFp = {{`Q_NE-`D_NE{1'b0}}, {`D_NE{1'b1}}}; - end - 2'h0: begin - MaxExpFp = {{`Q_NE-`S_NE{1'b0}}, {`S_NE{1'b1}}}; - end - 2'h2: begin - MaxExpFp = {{`Q_NE-`H_NE{1'b0}}, {`H_NE{1'b1}}}; - end + `Q_FMT: ResExpGteMax = &FullResExp[`Q_NE-1:0] | FullResExp[`Q_NE]; + `D_FMT: ResExpGteMax = &FullResExp[`D_NE-1:0] | (|FullResExp[`Q_NE:`D_NE]); + `S_FMT: ResExpGteMax = &FullResExp[`S_NE-1:0] | (|FullResExp[`Q_NE:`S_NE]); + `H_FMT: ResExpGteMax = &FullResExp[`H_NE-1:0] | (|FullResExp[`Q_NE:`H_NE]); endcase - assign MaxExp = ToInt&CvtOp ? Int64 ? (`NE)'(65) : (`NE)'(33) : MaxExpFp; + // a left shift of intlen+1 is still in range but any more than that is an overflow + // inital: | 64 0's | XLEN | + // | 64 0's | XLEN | << 64 + // | XLEN | 00000... | + // 65 = ...0 0 0 0 0 1 0 0 0 0 0 1 + // | or | | or | + // 33 = ...0 0 0 0 0 0 1 0 0 0 0 1 + // | or | | or | + // larger or equal if: + // - any of the bits after the most significan 1 is one + // - the most signifcant in 65 or 33 is still a one in the number and + // one of the later bits is one + assign ShiftGtIntSz = (|FullResExp[`Q_NE:7]|(FullResExp[6]&~Int64)) | ((|FullResExp[4:0]|(FullResExp[5]&Int64))&((FullResExp[5]&~Int64) | FullResExp[6]&Int64)); end - // if the result is greater than or equal to the max exponent - // | and the exponent isn't negitive - // | | if the input isnt infinity or NaN - // | | | - assign Overflow = (FullResExp>={2'b0, MaxExp}) & ~FullResExp[`NE+1]&~(InfIn|NaNIn); + // if the result is greater than or equal to the max exponent(not taking into account sign) + // | and the exponent isn't negitive + // | | if the input isnt infinity or NaN + // | | | + assign Overflow = ResExpGteMax & ~FullResExp[`NE+1]&~(InfIn|NaNIn); // detecting tininess after rounding // the exponent is negitive @@ -123,12 +119,12 @@ module flags( // if the input is NaN or infinity // | if the integer res overflows (out of range) - // | | if the input was negitive but ouputing to a unsigned number - // | | | the res doesn't round to zero - // | | | | or the res rounds up out of bounds - // | | | | and the res didn't underflow - // | | | | | - assign IntInvalid = XNaNM|XInfM|Overflow|((XSgnM&~Signed)&(~((CvtCalcExpM[`NE]|(~|CvtCalcExpM))&~Plus1)))|(NegResMSBS[1]^NegResMSBS[0]); + // | | if the input was negitive but ouputing to a unsigned number + // | | | the res doesn't round to zero + // | | | | or the res rounds up out of bounds + // | | | | and the res didn't underflow + // | | | | | + assign IntInvalid = XNaNM|XInfM|(ShiftGtIntSz&~FullResExp[`NE+1])|((XSgnM&~Signed)&(~((CvtCalcExpM[`NE]|(~|CvtCalcExpM))&~Plus1)))|(NegResMSBS[1]^NegResMSBS[0]); // | // or when the positive res rounds up out of range assign SigNaN = (XSNaNM&~(IntToFp&CvtOp)) | (YSNaNM&~CvtOp) | (ZSNaNM&FmaOp); diff --git a/pipelined/src/fpu/fmashiftcalc.sv b/pipelined/src/fpu/fmashiftcalc.sv index 755f4c2ce..17a13dda5 100644 --- a/pipelined/src/fpu/fmashiftcalc.sv +++ b/pipelined/src/fpu/fmashiftcalc.sv @@ -25,7 +25,7 @@ module fmashiftcalc( assign SumZero = ~(|SumM); // calculate the sum's exponent - assign NormSumExp = KillProdM ? {2'b0, ZExpM[`NE-1:1], ZExpM[0]&~ZDenormM} : ProdExpM + -({{`NE+2-$unsigned($clog2(3*`NF+7)){1'b0}}, FmaNormCntM} + 1 - (`NE+2)'(`NF+4)); + assign NormSumExp = KillProdM ? {2'b0, ZExpM[`NE-1:1], ZExpM[0]&~ZDenormM} : ProdExpM + -{{`NE+2-$unsigned($clog2(3*`NF+7)){1'b0}}, FmaNormCntM} - 1 + (`NE+2)'(`NF+4); //convert the sum's exponent into the propper percision if (`FPSIZES == 1) begin @@ -40,7 +40,7 @@ module fmashiftcalc( `FMT: ConvNormSumExp = NormSumExp; `FMT1: ConvNormSumExp = (NormSumExp-(`NE+2)'(`BIAS)+(`NE+2)'(`BIAS1))&{`NE+2{|NormSumExp}}; `FMT2: ConvNormSumExp = (NormSumExp-(`NE+2)'(`BIAS)+(`NE+2)'(`BIAS2))&{`NE+2{|NormSumExp}}; - default: ConvNormSumExp = `NE+2'bx; + default: ConvNormSumExp = {`NE+2{1'bx}}; endcase end diff --git a/pipelined/src/fpu/fsgninj.sv b/pipelined/src/fpu/fsgninj.sv index 120d9aa55..0a3a3454f 100755 --- a/pipelined/src/fpu/fsgninj.sv +++ b/pipelined/src/fpu/fsgninj.sv @@ -46,7 +46,7 @@ module fsgninj ( // // calculate the result's sign - assign ResSgn = SgnOpCodeE[1] ? (XSgnE ^ YSgnE) : (YSgnE ^ SgnOpCodeE[0]); + assign ResSgn = (SgnOpCodeE[1] ? XSgnE : SgnOpCodeE[0]) ^ YSgnE; // format final result based on precision // - uses NaN-blocking format @@ -64,7 +64,7 @@ module fsgninj ( `FMT: SgnResE = {ResSgn, FSrcXE[`FLEN-2:0]}; `FMT1: SgnResE = {{`FLEN-`LEN1{1'b1}}, ResSgn, FSrcXE[`LEN1-2:0]}; `FMT2: SgnResE = {{`FLEN-`LEN2{1'b1}}, ResSgn, FSrcXE[`LEN2-2:0]}; - default: SgnResE = 0; + default: SgnResE = {`FLEN{1'bx}}; endcase else if (`FPSIZES == 4) diff --git a/pipelined/src/fpu/postprocess.sv b/pipelined/src/fpu/postprocess.sv index 06902aa5c..4cee7147e 100644 --- a/pipelined/src/fpu/postprocess.sv +++ b/pipelined/src/fpu/postprocess.sv @@ -82,7 +82,7 @@ module postprocess( logic PreResultDenorm; // is the result denormalized - calculated before LZA corection logic [$clog2(3*`NF+7)-1:0] FmaShiftAmt; // normalization shift count logic [$clog2(`NORMSHIFTSZ)-1:0] ShiftAmt; // normalization shift count - logic [3*`NF+8:0] ShiftIn; // is the sum zero + logic [`NORMSHIFTSZ-1:0] ShiftIn; // is the sum zero logic [`NORMSHIFTSZ-1:0] Shifted; // the shifted result logic Plus1; // add one to the final result? logic IntInvalid, Overflow, Underflow, Invalid; // flags @@ -150,8 +150,8 @@ module postprocess( ShiftIn = 0;//{{`NORMSHIFTSZ-(3*`NF+8){1'b0}}, DivShiftIn}; end default: begin - ShiftAmt = 0; - ShiftIn = 0; + ShiftAmt = {$clog2(`NORMSHIFTSZ){1'bx}}; + ShiftIn = {`NORMSHIFTSZ{1'bx}}; end endcase diff --git a/pipelined/src/fpu/unpackinput.sv b/pipelined/src/fpu/unpackinput.sv index eaaebc500..1246eab0a 100644 --- a/pipelined/src/fpu/unpackinput.sv +++ b/pipelined/src/fpu/unpackinput.sv @@ -98,7 +98,7 @@ module unpackinput ( `FMT: BadNaNBox = 0; `FMT1: BadNaNBox = ~&In[`FLEN-1:`LEN1]; `FMT2: BadNaNBox = ~&In[`FLEN-1:`LEN2]; - default: BadNaNBox = 0; + default: BadNaNBox = 1'bx; endcase // extract the sign bit @@ -107,7 +107,7 @@ module unpackinput ( `FMT: Sgn = In[`FLEN-1]; `FMT1: Sgn = In[`LEN1-1]; `FMT2: Sgn = In[`LEN2-1]; - default: Sgn = 0; + default: Sgn = 1'bx; endcase // extract the fraction @@ -116,7 +116,7 @@ module unpackinput ( `FMT: Frac = In[`NF-1:0]; `FMT1: Frac = {In[`NF1-1:0], (`NF-`NF1)'(0)}; `FMT2: Frac = {In[`NF2-1:0], (`NF-`NF2)'(0)}; - default: Frac = 0; + default: Frac = {`NF{1'bx}}; endcase // is the exponent non-zero @@ -125,7 +125,7 @@ module unpackinput ( `FMT: ExpNonZero = |In[`FLEN-2:`NF]; // if input is largest precision (`FLEN - ie quad or double) `FMT1: ExpNonZero = |In[`LEN1-2:`NF1]; // if input is larger precsion (`LEN1 - double or single) `FMT2: ExpNonZero = |In[`LEN2-2:`NF2]; // if input is smallest precsion (`LEN2 - single or half) - default: ExpNonZero = 0; + default: ExpNonZero = 1'bx; endcase // example double to single conversion: @@ -142,7 +142,7 @@ module unpackinput ( `FMT: Exp = {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero}; `FMT1: Exp = {In[`LEN1-2], {`NE-`NE1{~In[`LEN1-2]}}, In[`LEN1-3:`NF1+1], In[`NF1]|~ExpNonZero}; `FMT2: Exp = {In[`LEN2-2], {`NE-`NE2{~In[`LEN2-2]}}, In[`LEN2-3:`NF2+1], In[`NF2]|~ExpNonZero}; - default: Exp = 0; + default: Exp = {`NE{1'bx}}; endcase // is the exponent all 1's @@ -151,7 +151,7 @@ module unpackinput ( `FMT: ExpMax = &In[`FLEN-2:`NF]; `FMT1: ExpMax = &In[`LEN1-2:`NF1]; `FMT2: ExpMax = &In[`LEN2-2:`NF2]; - default: ExpMax = 0; + default: ExpMax = 1'bx; endcase end else if (`FPSIZES == 4) begin // if all precsisons are supported - quad, double, single, and half