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https://github.com/openhwgroup/cvw
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Fixed the CacheHit logger bug.
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parent
6e37977c8f
commit
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@ -153,7 +153,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
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end
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end
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string AccessTypeString, HitMissString;
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string AccessTypeString, HitMissString;
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always @(*) begin
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always @(*) begin
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HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" :
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HitMissString = dut.core.ifu.bus.icache.icache.Hit ? "H" :
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dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
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dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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@ -178,7 +178,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
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flop #(1) ResetDReg(clk, reset, resetD);
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flop #(1) ResetDReg(clk, reset, resetD);
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assign resetEdge = ~reset & resetD;
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assign resetEdge = ~reset & resetD;
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always @(*) begin
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always @(*) begin
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HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" :
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HitMissString = dut.core.lsu.bus.dcache.dcache.Hit ? "H" :
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(!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
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(!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
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dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
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dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
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AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
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AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
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