diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv
index bd387f5d7..430750c71 100755
--- a/src/fpu/fpu.sv
+++ b/src/fpu/fpu.sv
@@ -155,7 +155,7 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
   logic [P.FLEN-1:0]           FResultW;                           // final FP result being written to the FP register   
 
   // other signals
-  logic [P.FLEN-1:0]           AlignedSrcAE;                       // align SrcA from IEU to the floating point format for fmv
+  logic [P.FLEN-1:0]           PreIntSrcE, IntSrcE;                // align SrcA from IEU to the floating point format for fmv / fmvp
   logic [P.FLEN-1:0]           BoxedZeroE;                         // Zero value for Z for multiplication, with NaN boxing if needed
   logic [P.FLEN-1:0]           BoxedOneE;                          // One value for Z for multiplication, with NaN boxing if needed
   logic                        StallUnpackedM;                     // Stall unpacker outputs during multicycle fdivsqrt
@@ -273,23 +273,27 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
     fli #(P) fli(.Rs1(Rs1E), .Fmt(FmtE), .Imm(FliResE)); 
   end else assign FliResE = '0;
 
-  // NaN Box SrcA to convert integer to requested FP size for fmv.*.x
-  if(P.FPSIZES == 1) assign AlignedSrcAE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
+  // fmv.*.x: NaN Box SrcA to extend integer to requested FP size 
+  if(P.FPSIZES == 1) assign PreIntSrcE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
   else if(P.FPSIZES == 2) 
-    mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
+    mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, PreIntSrcE);
   else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin
     localparam XD_LEN = P.D_LEN < P.XLEN ? P.D_LEN : P.XLEN; // shorter of D_LEN and XLEN
     mux3 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]}, 
                             {{P.FLEN-XD_LEN{1'b1}}, ForwardedSrcAE[XD_LEN-1:0]}, 
                             {{P.FLEN-P.H_LEN{1'b1}}, ForwardedSrcAE[P.H_LEN-1:0]}, 
-                            FmtE, AlignedSrcAE); // NaN boxing zeroes
+                            FmtE, PreIntSrcE); // NaN boxing zeroes
   end
+  // fmvp.*.x: Select pair of registers
+  if (P.ZFA_SUPPORTED & (P.XLEN==32 & P.D_SUPPORTED) | (P.XLEN==64 & P.Q_SUPPORTED))
+       assign IntSrcE = ZfaE ? {ForwardedSrcBE, ForwardedSrcAE} : PreIntSrcE; // choose pair of integer registers for fmvp.d.x / fmvp.q.x
+  else assign IntSrcE = PreIntSrcE;
 
   // select a result that may be written to the FP register
-  mux4  #(P.FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, FliResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
+  mux4  #(P.FLEN) FResMux(SgnResE, IntSrcE, CmpFpResE, FliResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
   assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE);
 
-  // select the result that may be written to the integer register with fmv.x.*
+  // fmv.x.*: select the result that may be written to the integer register
   if(P.FPSIZES == 1) begin
     assign mvsgn = XE[P.FLEN-1];
     assign SgnExtXE = XE;
diff --git a/testbench/tests.vh b/testbench/tests.vh
index 43cbc91a0..0c60228dd 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -2004,6 +2004,8 @@ string arch64zbs[] = '{
     "rv32i_m/F_Zfa/src/fli.s-01.S",
     "rv32i_m/F_Zfa/src/fltq_b1-01.S",
     "rv32i_m/F_Zfa/src/fltq_b19-01.S",
+    "rv32i_m/D_Zfa/src/fltq_b1-01.S", // these D tests are more comprehensive and seem they should replace the F tests.  Applies to all F tests duplicated in D
+    "rv32i_m/D_Zfa/src/fltq_b19-01.S",
     "rv32i_m/F_Zfa/src/fminm_b1-01.S",
     "rv32i_m/F_Zfa/src/fminm_b19-01.S",
     "rv32i_m/F_Zfa/src/fmaxm_b1-01.S",
@@ -2015,13 +2017,21 @@ string arch64zbs[] = '{
     `RISCVARCHTEST,
     "rv32i_m/D_Zfa/src/fleq_b1-01.S",
     "rv32i_m/D_Zfa/src/fleq_b19-01.S", 
+    "rv32i_m/D_Zfa/src/fleq.d_b1-01.S",
+    "rv32i_m/D_Zfa/src/fleq.d_b19-01.S", 
     "rv32i_m/D_Zfa/src/fli.d-01.S",
     "rv32i_m/D_Zfa/src/fltq_b1-01.S",
     "rv32i_m/D_Zfa/src/fltq_b19-01.S",
+    "rv32i_m/D_Zfa/src/fltq.d_b1-01.S",
+    "rv32i_m/D_Zfa/src/fltq.d_b19-01.S",
     "rv32i_m/D_Zfa/src/fminm_b1-01.S",
     "rv32i_m/D_Zfa/src/fminm_b19-01.S",
+    "rv32i_m/D_Zfa/src/fminm.d_b1-01.S",
+    "rv32i_m/D_Zfa/src/fminm.d_b19-01.S",
     "rv32i_m/D_Zfa/src/fmaxm_b1-01.S",
-    "rv32i_m/D_Zfa/src/fmaxm_b19-01.S"
+    "rv32i_m/D_Zfa/src/fmaxm_b19-01.S",
+    "rv32i_m/D_Zfa/src/fmaxm.d_b1-01.S",
+    "rv32i_m/D_Zfa/src/fmaxm.d_b19-01.S"
 /*    "rv32i_m/D_Zfa/src/fround_b1-01.S" */
   };