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Reset MSR on read

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This commit is contained in:
David Harris 2022-07-22 04:29:27 +00:00
parent 28c61a2191
commit 07c946bb04
1 changed files with 2 additions and 0 deletions
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pipelined/src/uncore/uartPC16550D.sv
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@ -206,6 +206,8 @@ module uartPC16550D(
// Modem Status Register (8.6.8)
if (~MEMWb & (A == 3'b110))
MSR <= #1 Din[3:0];
else if (~MEMRb & (A == 3'b110))
MSR <= #1 4'b0; // Reading MSR clears the flags in MSR bits 3:0
else begin
MSR[0] <= #1 MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send
MSR[1] <= #1 MSR[1] | DSRb2 ^ DSRbsync; // Delta Data Set Ready