diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv index 006b1b72e..f1cb9e0b8 100644 --- a/wally-pipelined/src/privileged/csrc.sv +++ b/wally-pipelined/src/privileged/csrc.sv @@ -27,11 +27,11 @@ /////////////////////////////////////////// `include "wally-config.vh" -// Ben 06/17/21: I brought in MTIME, MTIMECMP from CLINT. *** this probably isn't perfect though because it doesn't yet provide the ability to change these through CSR writes +// Ben 06/17/21: I brought in MTIME, MTIMECMP from CLINT. *** this probably isn't perfect though because it doesn't yet provide the ability to change these through CSR writes; overall this whole thing might need some rethinking module csrc #(parameter MCYCLE = 12'hB00, - // MTIME = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive - // MTIMECMP = 12'hB21, // not specified in privileged spec. Move to CLINT + MTIMEadr = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive + MTIMECMPadr = 12'hB21, // not specified in privileged spec. Move to CLINT MINSTRET = 12'hB02, MHPMCOUNTERBASE = 12'hB00, //MHPMCOUNTER3 = 12'hB03, @@ -39,8 +39,8 @@ module csrc #(parameter // ... more counters //MHPMCOUNTER31 = 12'hB1F, MCYCLEH = 12'hB80, - // MTIMEH = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive - // MTIMECMPH = 12'hBA1, // not specified in privileged spec. Move to CLINT + MTIMEHadr = 12'hB81, // address not specified in privileged spec. Consider moving to CLINT to match SiFive + MTIMECMPHadr = 12'hBA1, // not specified in privileged spec. Move to CLINT MINSTRETH = 12'hB82, MHPMCOUNTERHBASE = 12'hB80, //MHPMCOUNTER3H = 12'hB83, @@ -230,8 +230,8 @@ module csrc #(parameter if (CSRAdrM >= MHPMCOUNTERBASE+3 && CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-MHPMCOUNTERBASE]; else if (CSRAdrM >= HPMCOUNTERBASE+3 && CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CSRAdrM-HPMCOUNTERBASE]; else case (CSRAdrM) - // MTIME: CSRCReadValM = TIME_REGW; - // MTIMECMP: CSRCReadValM = TIMECMP_REGW; + MTIMEadr: CSRCReadValM = MTIME; + MTIMECMPadr: CSRCReadValM = MTIMECMP; MCYCLE: CSRCReadValM = CYCLE_REGW; MINSTRET: CSRCReadValM = INSTRET_REGW; //MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW; @@ -259,8 +259,8 @@ module csrc #(parameter else if (CSRAdrM >= MHPMCOUNTERHBASE+3 && CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-MHPMCOUNTERHBASE]; else if (CSRAdrM >= HPMCOUNTERHBASE+3 && CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CSRAdrM-HPMCOUNTERHBASE]; else case (CSRAdrM) - // MTIME: CSRCReadValM = TIME_REGW[31:0]; - // MTIMECMP: CSRCReadValM = TIMECMP_REGW[31:0]; + MTIMEadr: CSRCReadValM = MTIME[31:0]; + MTIMECMPadr: CSRCReadValM = MTIMECMP[31:0]; MCYCLE: CSRCReadValM = CYCLE_REGW[31:0]; MINSTRET: CSRCReadValM = INSTRET_REGW[31:0]; //MHPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0]; @@ -270,8 +270,8 @@ module csrc #(parameter INSTRET: CSRCReadValM = INSTRET_REGW[31:0]; //HPMCOUNTER3: CSRCReadValM = HPMCOUNTER3_REGW[31:0]; //HPMCOUNTER4: CSRCReadValM = HPMCOUNTER4_REGW[31:0]; - // MTIMEH: CSRCReadValM = TIME_REGW[63:32]; - // MTIMECMPH: CSRCReadValM = TIMECMP_REGW[63:32]; + MTIMEHadr: CSRCReadValM = MTIME[63:32]; + MTIMECMPHadr: CSRCReadValM = MTIMECMP[63:32]; MCYCLEH: CSRCReadValM = CYCLE_REGW[63:32]; MINSTRETH: CSRCReadValM = INSTRET_REGW[63:32]; //MHPMCOUNTER3H: CSRCReadValM = HPMCOUNTER3_REGW[63:32];