From 0737efc86c05643458e4829ad7221760222a6703 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 5 Jan 2023 13:36:51 -0600 Subject: [PATCH] More branch predictor cleanup. --- pipelined/src/ifu/bpred.sv | 37 ++++++----------------- pipelined/src/ifu/ifu.sv | 6 ++-- pipelined/src/privileged/csr.sv | 4 +-- pipelined/src/privileged/csrc.sv | 4 +-- pipelined/src/privileged/privileged.sv | 4 +-- pipelined/src/wally/wallypipelinedcore.sv | 6 ++-- 6 files changed, 21 insertions(+), 40 deletions(-) diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index bf5582371..edf974cb8 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -60,14 +60,14 @@ module bpred ( // Report branch prediction status output logic BPPredWrongE, // Prediction is wrong. - output logic BPPredDirWrongM, // Prediction direction is wrong. + output logic DirPredictionWrongM, // Prediction direction is wrong. output logic BTBPredPCWrongM, // Prediction target wrong. output logic RASPredPCWrongM, // RAS prediction is wrong. output logic BPPredClassNonCFIWrongM // Class prediction is wrong. ); logic BTBValidF; - logic [1:0] DirPredictionF, DirPredictionD, DirPredictionE, UpdateBPPredE; + logic [1:0] DirPredictionF; logic [4:0] BPInstrClassF, BPInstrClassD, BPInstrClassE; logic [`XLEN-1:0] BTBPredPCF, RASPCF; @@ -76,7 +76,7 @@ module bpred ( logic PredictionPCWrongE; logic PredictionInstrClassWrongE; logic [4:0] InstrClassD, InstrClassE; - logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; + logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; logic SelBPPredF; logic [`XLEN-1:0] BPPredPCF; @@ -88,17 +88,17 @@ module bpred ( // look into the 2 port Sram model. something is wrong. if (`BPTYPE == "BPTWOBIT") begin:Predictor twoBitPredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PCNextF, .PCM, .DirPredictionF(DirPredictionF), .DirPredictionWrongE(BPPredDirWrongE), + .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPTYPE == "BPGLOBAL") begin:Predictor globalhistory DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PCNextF, .PCM, .DirPredictionF(DirPredictionF), .DirPredictionWrongE(BPPredDirWrongE), + .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPTYPE == "BPGSHARE") begin:Predictor gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PCNextF, .PCM, .DirPredictionF(DirPredictionF), .DirPredictionWrongE(BPPredDirWrongE), + .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPTYPE == "BPLOCALPAg") begin:Predictor @@ -154,22 +154,6 @@ module bpred ( assign BPPredPCF = BPInstrClassF[3] ? RASPCF : BTBPredPCF; - // The prediction and its results need to be passed through the pipeline - // *** for other predictors will will be different. - // *** should these be flushed? - flopenr #(2) BPPredRegD(.clk(clk), - .reset(reset), - .en(~StallD), - .d(DirPredictionF), - .q(DirPredictionD)); - - flopenr #(2) BPPredRegE(.clk(clk), - .reset(reset), - .en(~StallE), - .d(DirPredictionD), - .q(DirPredictionE)); - - // the branch predictor needs a compact decoding of the instruction class. // *** consider adding in the alternate return address x5 for returns. assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5 @@ -183,8 +167,8 @@ module bpred ( // branch predictor flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, - {BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE}, - {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM}); + {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE}, + {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM}); // pipeline the class flopenrc #(5) BPInstrClassRegD(clk, reset, FlushD, ~StallD, BPInstrClassF, BPInstrClassD); @@ -202,7 +186,7 @@ module bpred ( // The branch direction also need to checked. // However if the direction is wrong then the pc will be wrong. This is only relavent to checking the // accuracy of the direciton prediction. - //assign BPPredDirWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0]; + //assign DirPredictionWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0]; // Finally we need to check if the class is wrong. When the class is wrong the BTB needs to be updated. // Also we want to track this in a performance counter. @@ -220,9 +204,6 @@ module bpred ( // Finally if the real instruction class is non CFI but the predictor said it was we need to count. assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE; - // 2 bit saturating counter - satCounter2 BPDirUpdate(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(UpdateBPPredE)); - // Selects the BP or PC+2/4. mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F); // If the prediction is wrong select the correct address. diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index d08bffcfc..8d1b71cc6 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -62,7 +62,7 @@ module ifu ( output logic [`XLEN-1:0] PCM, // branch predictor output logic [4:0] InstrClassM, - output logic BPPredDirWrongM, + output logic DirPredictionWrongM, output logic BTBPredPCWrongM, output logic RASPredPCWrongM, output logic BPPredClassNonCFIWrongM, @@ -325,12 +325,12 @@ module ifu ( .FlushD, .FlushE, .FlushM, .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, - .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); + .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); end else begin : bpred mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PCNext1F)); assign BPPredWrongE = PCSrcE; - assign {InstrClassM, BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0; + assign {InstrClassM, DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0; assign PCNext0F = PCPlus2or4F; assign NextValidPCE = PCE; end diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index e54bd04aa..608fe2744 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -45,7 +45,7 @@ module csr #(parameter input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, input logic InstrValidM, FRegWriteM, LoadStallD, - input logic BPPredDirWrongM, + input logic DirPredictionWrongM, input logic BTBPredPCWrongM, input logic RASPredPCWrongM, input logic BPPredClassNonCFIWrongM, @@ -214,7 +214,7 @@ module csr #(parameter csrc counters(.clk, .reset, .StallE, .StallM, .StallW, .FlushM, .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM, - .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, + .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .CSRAdrM, .PrivilegeModeW, .CSRWriteValM, .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW, diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index e57fdfc72..d55b6cadb 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -45,7 +45,7 @@ module csrc #(parameter input logic StallE, StallM, StallW, input logic FlushM, input logic InstrValidNotFlushedM, LoadStallD, CSRMWriteM, - input logic BPPredDirWrongM, + input logic DirPredictionWrongM, input logic BTBPredPCWrongM, input logic RASPredPCWrongM, input logic BPPredClassNonCFIWrongM, @@ -86,7 +86,7 @@ module csrc #(parameter assign CounterEvent[`COUNTERS-1:3] = 0; end else begin: cevent // User-defined counters assign CounterEvent[3] = LoadStallM; // don't want to suppress on flush as this only happens if flushed. - assign CounterEvent[4] = BPPredDirWrongM & InstrValidNotFlushedM; + assign CounterEvent[4] = DirPredictionWrongM & InstrValidNotFlushedM; assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM; assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM; assign CounterEvent[7] = (InstrClassM[4] | InstrClassM[2] | InstrClassM[1]) & InstrValidNotFlushedM; diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index b8985abb0..18c0a82e3 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -41,7 +41,7 @@ module privileged ( output logic sfencevmaM, input logic InstrValidM, CommittedM, CommittedF, input logic FRegWriteM, LoadStallD, - input logic BPPredDirWrongM, + input logic DirPredictionWrongM, input logic BTBPredPCWrongM, input logic RASPredPCWrongM, input logic BPPredClassNonCFIWrongM, @@ -128,7 +128,7 @@ module privileged ( .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, - .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, + .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 24ef3dbef..515cabe72 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -148,7 +148,7 @@ module wallypipelinedcore ( logic LSUHREADY; logic BPPredWrongE; - logic BPPredDirWrongM; + logic DirPredictionWrongM; logic BTBPredPCWrongM; logic RASPredPCWrongM; logic BPPredClassNonCFIWrongM; @@ -184,7 +184,7 @@ module wallypipelinedcore ( // Mem .RetM, .TrapM, .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, - .InstrD, .InstrM, .PCM, .InstrClassM, .BPPredDirWrongM, + .InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, // Writeback @@ -340,7 +340,7 @@ module wallypipelinedcore ( .sfencevmaM, .InstrValidM, .CommittedM, .CommittedF, .FRegWriteM, .LoadStallD, - .BPPredDirWrongM, .BTBPredPCWrongM, + .DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,