From 06efd2cdde2aeb883c64d25324bccf9f878f47b0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 31 Jul 2023 14:13:09 -0500 Subject: [PATCH] Pushed performance of arty a7 to 23Mhz. --- fpga/constraints/marked_debug.txt | 134 ++---------------------------- fpga/generator/wally.tcl | 2 +- fpga/generator/xlnx_mmcm.tcl | 2 +- linux/devicetree/wally-artya7.dts | 12 +-- 4 files changed, 13 insertions(+), 137 deletions(-) diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index 3973fc451..9b7927e10 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -1,131 +1,7 @@ -lsu/lsu.sv: logic IEUAdrM -lsu/lsu.sv: logic WriteDataM -lsu/lsu.sv: logic LSUHADDR -lsu/lsu.sv: logic HRDATA -lsu/lsu.sv: logic LSUHWDATA -lsu/lsu.sv: logic LSUHREADY -lsu/lsu.sv: logic LSUHWRITE -lsu/lsu.sv: logic LSUHSIZE -lsu/lsu.sv: logic LSUHBURST -lsu/lsu.sv: logic LSUHTRANS -lsu/lsu.sv: logic LSUHWSTRB -lsu/lsu.sv: logic IHAdrM -ieu/regfile.sv: logic rf -ieu/datapath.sv: logic RegWriteW -hazard/hazard.sv: logic BPPredWrongE -hazard/hazard.sv: logic LoadStallD -hazard/hazard.sv: logic FCvtIntStallD -hazard/hazard.sv: logic DivBusyE -hazard/hazard.sv: logic EcallFaultM -hazard/hazard.sv: logic WFIStallM -hazard/hazard.sv: logic StallF -hazard/hazard.sv: logic FlushD -cache/cachefsm.sv: statetype CurrState -wally/wallypipelinedcore.sv: logic TrapM -wally/wallypipelinedcore.sv: logic SrcAM -wally/wallypipelinedcore.sv: logic InstrM wally/wallypipelinedcore.sv: logic PCM -wally/wallypipelinedcore.sv: logic MemRWM +wally/wallypipelinedcore.sv: logic TrapM wally/wallypipelinedcore.sv: logic InstrValidM -wally/wallypipelinedcore.sv: logic WriteDataM -wally/wallypipelinedcore.sv: logic IEUAdrM -wally/wallypipelinedcore.sv: logic HRDATA -ifu/spill.sv: statetype CurrState -ifu/ifu.sv: logic IFUStallF -ifu/ifu.sv: logic IFUHADDR -ifu/ifu.sv: logic HRDATA -ifu/ifu.sv: logic IFUHREADY -ifu/ifu.sv: logic IFUHWRITE -ifu/ifu.sv: logic IFUHSIZE -ifu/ifu.sv: logic IFUHBURST -ifu/ifu.sv: logic IFUHTRANS -ifu/ifu.sv: logic PCF -ifu/ifu.sv: logic PCNextF -ifu/ifu.sv: logic PCPF -ifu/ifu.sv: logic PostSpillInstrRawF -mmu/hptw.sv: logic ITLBWriteF -mmu/hptw.sv: statetype WalkerState -privileged/csrs.sv: logic CSRSReadValM -privileged/csrs.sv: logic SEPC_REGW -privileged/csrs.sv: logic MIP_REGW -privileged/csrs.sv: logic SSCRATCH_REGW -privileged/csrs.sv: logic SCAUSE_REGW -privileged/csr.sv: logic CSRReadValM -privileged/csr.sv: logic CSRSrcM -privileged/csr.sv: logic CSRWriteValM -privileged/csr.sv: logic MSTATUS_REGW -privileged/trap.sv: logic InstrMisalignedFaultM -privileged/trap.sv: logic BreakpointFaultM -privileged/trap.sv: logic LoadAccessFaultM -privileged/trap.sv: logic LoadPageFaultM -privileged/trap.sv: logic mretM -privileged/trap.sv: logic MIP_REGW -privileged/trap.sv: logic PendingIntsM -privileged/privileged.sv: logic CSRReadM -privileged/privileged.sv: logic InterruptM -privileged/csrc.sv: logic HPMCOUNTER_REGW -privileged/csri.sv: logic MExtInt -privileged/csri.sv: logic MIP_REGW_writeabl -privileged/csrm.sv: logic MIP_REGW -privileged/csrm.sv: logic MEPC_REGW -privileged/csrm.sv: logic MEDELEG_REGW -privileged/csrm.sv: logic MIDELEG_REGW -privileged/csrm.sv: logic MSCRATCH_REGW -privileged/csrm.sv: logic MCAUSE_REGW -uncore/uart_apb.sv: logic SIN -uncore/uart_apb.sv: logic SOUT -uncore/uart_apb.sv: logic OUT1b -uncore/uartPC16550D.sv: logic RBR -uncore/uartPC16550D.sv: logic FCR -uncore/uartPC16550D.sv: logic IER -uncore/uartPC16550D.sv: logic MCR -uncore/uartPC16550D.sv: logic baudpulse -uncore/uartPC16550D.sv: statetype rxstate -uncore/uartPC16550D.sv: logic rxfifo -uncore/uartPC16550D.sv: logic txfifo -uncore/uartPC16550D.sv: logic rxfifohead -uncore/uartPC16550D.sv: logic rxfifoentries -uncore/uartPC16550D.sv: logic RXBR -uncore/uartPC16550D.sv: logic rxtimeoutcnt -uncore/uartPC16550D.sv: logic rxparityerr -uncore/uartPC16550D.sv: logic rxdataready -uncore/uartPC16550D.sv: logic rxfifoempty -uncore/uartPC16550D.sv: logic rxdata -uncore/uartPC16550D.sv: logic RXerrbit -uncore/uartPC16550D.sv: logic rxfullbitunwrapped -uncore/uartPC16550D.sv: logic txdata -uncore/uartPC16550D.sv: logic txnextbit -uncore/uartPC16550D.sv: logic txfifoempty -uncore/uartPC16550D.sv: logic fifoenabled -uncore/uartPC16550D.sv: logic RXerr -uncore/uartPC16550D.sv: logic THRE -uncore/uartPC16550D.sv: logic rxdataavailintr -uncore/uartPC16550D.sv: logic intrID -uncore/uncore.sv: logic HSELEXTSDCD -uncore/plic_apb.sv: logic MExtInt -uncore/plic_apb.sv: logic Din -uncore/plic_apb.sv: logic requests -uncore/plic_apb.sv: logic intPriority -uncore/plic_apb.sv: logic intInProgress -uncore/plic_apb.sv: logic intThreshold -uncore/plic_apb.sv: logic intEn -uncore/plic_apb.sv: logic intClaim -uncore/plic_apb.sv: logic irqMatrix -uncore/plic_apb.sv: logic priorities_with_irqs -uncore/plic_apb.sv: logic max_priority_with_irqs -uncore/plic_apb.sv: logic irqs_at_max_priority -uncore/plic_apb.sv: logic threshMask -uncore/clint_apb.sv: logic MTIME -uncore/clint_apb.sv: logic MTIMECMP -ebu/ebu.sv: logic HCLK -ebu/ebu.sv: logic HREADY -ebu/ebu.sv: logic HRESP -ebu/ebu.sv: logic HADDR -ebu/ebu.sv: logic HWRITE -ebu/ebu.sv: logic HSIZE -ebu/ebu.sv: logic HBURST -ebu/ebu.sv: logic HPROT -ebu/ebu.sv: logic HTRANS -ebu/ebu.sv: logic HMASTLOC -ebu/buscachefsm.sv: busstatetype CurrState -ebu/busfsm.sv: busstatetype CurrState +wally/wallypipelinedcore.sv: logic InstrM +lsu/lsu.sv: logic LSUHADDR +lsu/lsu.sv: logic LSUHREADY +lsu/lsu.sv: logic LSUHWDATA diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index d4e3dc2df..a3c7eec47 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -69,7 +69,7 @@ exec rm -rf reports/* report_compile_order -constraints > reports/compile_order.rpt # this is elaboration not synthesis. -synth_design -rtl -name rtl_1 +synth_design -rtl -name rtl_1 -flatten_hierarchy full report_clocks -file reports/clocks.rpt diff --git a/fpga/generator/xlnx_mmcm.tcl b/fpga/generator/xlnx_mmcm.tcl index 2f003e7a5..a8a2fe568 100644 --- a/fpga/generator/xlnx_mmcm.tcl +++ b/fpga/generator/xlnx_mmcm.tcl @@ -15,7 +15,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \ CONFIG.CLKOUT4_USED {false} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {23} \ CONFIG.CLKIN1_JITTER_PS {10.0} \ ] [get_ips $ipName] diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts index ed1c9c85d..57b9599e5 100644 --- a/linux/devicetree/wally-artya7.dts +++ b/linux/devicetree/wally-artya7.dts @@ -21,8 +21,8 @@ cpus { #address-cells = <0x01>; #size-cells = <0x00>; - clock-frequency = <0x1312D00>; - timebase-frequency = <0x1312D00>; + clock-frequency = <0x15EF3C0>; + timebase-frequency = <0x15EF3C0>; cpu@0 { phandle = <0x01>; @@ -51,7 +51,7 @@ uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; - clock-frequency = <0x1312D00>; + clock-frequency = <0x15EF3C0>; reg = <0x00 0x10000000 0x00 0x100>; compatible = "ns16550a"; }; @@ -74,11 +74,11 @@ fifo-depth = <256>; bus-width = <4>; interrupt-parent = <0x03>; - clock = <0x1312D00>; - max-frequency = <0x1312D00>; + clock = <0x15EF3C0>; + max-frequency = <0x15EF3C0>; cap-sd-highspeed; cap-mmc-highspeed; - sdio; + no-sdio; }; clint@2000000 {