From 06e34b7be4fad872649d58b56f2c44da3349dd17 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Sat, 27 Apr 2024 06:25:24 -0700
Subject: [PATCH] Fixed byte enables for synthesis

---
 src/generic/mem/ram1p1rwbe.sv  |  3 ++-
 src/generic/mem/ram1p1rwe.sv   |  7 ++++---
 src/generic/mem/ram2p1r1wbe.sv | 19 ++++++++++---------
 3 files changed, 16 insertions(+), 13 deletions(-)

diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
index 4da48d760..a0dd5aef4 100644
--- a/src/generic/mem/ram1p1rwbe.sv
+++ b/src/generic/mem/ram1p1rwbe.sv
@@ -1,5 +1,6 @@
 ///////////////////////////////////////////
-// 1 port sram.
+// ram1p1r2be.sv
+// 1 port sram with byte enables
 //
 // Written: ross1728@gmail.com
 // Created: 3 May 2021
diff --git a/src/generic/mem/ram1p1rwe.sv b/src/generic/mem/ram1p1rwe.sv
index ff844ff22..a030d2aab 100644
--- a/src/generic/mem/ram1p1rwe.sv
+++ b/src/generic/mem/ram1p1rwe.sv
@@ -1,4 +1,5 @@
 ///////////////////////////////////////////
+// ram1p1rwe.sv
 // 1 port sram.
 //
 // Written: avercruysse@hmc.edu (Modified from ram1p1rwbe, by ross1728@gmail.com)
@@ -49,19 +50,19 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) (
     // 64 x 128-bit SRAM
     ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
       .A(addr), .D(din), 
-      .BWEB(0), .Q(dout));
+      .BWEB('0), .Q(dout));
     
   end else if ((USE_SRAM == 1) & (WIDTH == 44)  & (DEPTH == 64)) begin // RV64 cache tag
     // 64 x 44-bit SRAM
     ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
       .A(addr), .D(din), 
-      .BWEB(0), .Q(dout));
+      .BWEB('0), .Q(dout));
 
   end else if ((USE_SRAM == 1) & (WIDTH == 22)  & (DEPTH == 64)) begin // RV32 cache tag
     // 64 x 22-bit SRAM
     ram1p1rwbe_64x22 sram1 (.CLK(clk), .CEB(~ce), .WEB(~we),
       .A(addr), .D(din), 
-      .BWEB(0), .Q(dout));     
+      .BWEB('0), .Q(dout));     
     
     // ***************************************************************************
     // READ first SRAM model
diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv
index d711fce7a..c4cee8b7e 100644
--- a/src/generic/mem/ram2p1r1wbe.sv
+++ b/src/generic/mem/ram2p1r1wbe.sv
@@ -1,4 +1,5 @@
 ///////////////////////////////////////////
+// ram2p1r1wbe.sv
 // 2 port sram.
 //
 // Written: ross1728@gmail.com May 3, 2021
@@ -55,11 +56,11 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
     
     ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), 
       .CEBA(~ce1), .CEBB(~ce2),
-      .WEBA(0), .WEBB(~we2),            
+      .WEBA(1'b0), .WEBB(~we2),            
       .AA(ra1), .AB(wa2),
-      .DA(0),
+      .DA('0),
       .DB(wd2),
-      .BWEBA(0), .BWEBB('1),
+      .BWEBA('0), .BWEBB('1),
       .QA(rd1),
       .QB());
 
@@ -67,11 +68,11 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
     
     ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), 
       .CEBA(~ce1), .CEBB(~ce2),
-      .WEBA(0), .WEBB(~we2),            
+      .WEBA(1'b0), .WEBB(~we2),            
       .AA(ra1), .AB(wa2),
-      .DA(0),
+      .DA('0),
       .DB(wd2),
-      .BWEBA(0), .BWEBB('1),
+      .BWEBA('0), .BWEBB('1),
       .QA(rd1),
       .QB());      
 
@@ -95,12 +96,12 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
     assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]];      
     ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk), 
       .CEBA(~ce1), .CEBB(~ce2),
-      .WEBA(0), .WEBB(~we2),            
+      .WEBA(1'b0), .WEBB(~we2),            
       .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), 
       .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]),
-      .DA(0),
+      .DA('0),
       .DB(SRAMWriteData),
-      .BWEBA(0), .BWEBB(SRAMBitMask),
+      .BWEBA('0), .BWEBB(SRAMBitMask),
       .QA(SRAMReadData),
       .QB());