From 06c8c316823673906fc482ed108467a046df7c48 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 2 Aug 2023 13:02:28 -0500 Subject: [PATCH] Fixed constraint in VCU118. --- fpga/constraints/constraints-vcu118.xdc | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/fpga/constraints/constraints-vcu118.xdc b/fpga/constraints/constraints-vcu118.xdc index 7b70950a5..4d185f994 100644 --- a/fpga/constraints/constraints-vcu118.xdc +++ b/fpga/constraints/constraints-vcu118.xdc @@ -3,8 +3,6 @@ # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4. # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP. -create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] - ##### GPI #### set_property PACKAGE_PIN BB24 [get_ports {GPI[0]}] set_property PACKAGE_PIN BF22 [get_ports {GPI[1]}] @@ -106,6 +104,11 @@ set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK] set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}] set_property PACKAGE_PIN AV15 [get_ports SDCCLK] set_property PACKAGE_PIN AY15 [get_ports {SDCCmd}] + +set_property PACKAGE_PIN AT15 [get_ports {SDCCD}] +set_property IOSTANDARD LVCMOS18 [get_ports {SDCCD}] +set_property PULLUP true [get_ports {SDCCD}] + set_property PULLUP true [get_ports {SDCDat[3]}] set_property PULLUP true [get_ports {SDCDat[2]}] set_property PULLUP true [get_ports {SDCDat[1]}] @@ -113,17 +116,17 @@ set_property PULLUP true [get_ports {SDCDat[0]}] set_property PULLUP true [get_ports {SDCCmd}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}] +set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCDat[*]}] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 21.000 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}] +set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCCmd}] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 14.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 6.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK] +set_output_delay -clock [get_clocks mmcm_clkout1] 0.000 [get_ports SDCCLK]