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The clock gater was not implemented correctly. Now it is level sensitive to a low clock.

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This commit is contained in:
Ross Thompson 2021-06-01 15:05:22 -05:00
parent fe22fd2db8
commit 0670c57fd2
1 changed files with 1 additions and 1 deletions
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wally-pipelined/src/generic/clockgater.sv
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@ -38,7 +38,7 @@ module clockgater
logic enable_q; logic enable_q;
always @(E or SE) begin always @(~CLK) begin
enable_q <= E | SE; enable_q <= E | SE;
end end
assign ECLK = enable_q & CLK; assign ECLK = enable_q & CLK;