diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 53ea11538..b0d85e517 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -62,14 +62,14 @@ `define DTLB_ENTRIES 32 // Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_LINELENINBITS 256 `define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_BLOCKLENINBITS 256 +`define ICACHE_LINELENINBITS 256 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/pipelined/config/busybear/wally-config.vh b/pipelined/config/busybear/wally-config.vh index fc2868ecc..d9c61a852 100644 --- a/pipelined/config/busybear/wally-config.vh +++ b/pipelined/config/busybear/wally-config.vh @@ -60,14 +60,14 @@ `define DTLB_ENTRIES 32 // Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 2048 -`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_LINELENINBITS 256 `define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 1 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_BLOCKLENINBITS 256 +`define ICACHE_LINELENINBITS 256 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/pipelined/config/coremark/wally-config.vh b/pipelined/config/coremark/wally-config.vh index fa089a3d9..944c3a4a5 100644 --- a/pipelined/config/coremark/wally-config.vh +++ b/pipelined/config/coremark/wally-config.vh @@ -62,14 +62,14 @@ `define DTLB_ENTRIES 32 // Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 2048 -`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_LINELENINBITS 256 `define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 1 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_BLOCKLENINBITS 256 +`define ICACHE_LINELENINBITS 256 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/pipelined/config/coremark_bare/wally-config.vh b/pipelined/config/coremark_bare/wally-config.vh index b7061fd52..90d4a5e9f 100644 --- a/pipelined/config/coremark_bare/wally-config.vh +++ b/pipelined/config/coremark_bare/wally-config.vh @@ -63,13 +63,13 @@ `define DTLB_ENTRIES 32 // Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_LINELENINBITS 256 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_BLOCKLENINBITS 256 +`define ICACHE_LINELENINBITS 256 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index c2ef2446b..b3c87cc78 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -62,14 +62,14 @@ `define DTLB_ENTRIES 32 // Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_LINELENINBITS 256 `define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_BLOCKLENINBITS 256 +`define ICACHE_LINELENINBITS 256 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 06499180b..adda1c6c3 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -61,14 +61,14 @@ `define DTLB_ENTRIES 32 // Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_LINELENINBITS 256 `define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_BLOCKLENINBITS 256 +`define ICACHE_LINELENINBITS 256 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index ade57a71a..abce4e271 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -61,14 +61,14 @@ `define DTLB_ENTRIES 0 // Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_LINELENINBITS 256 `define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_BLOCKLENINBITS 256 +`define ICACHE_LINELENINBITS 256 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index d29349012..0a3ebc9c1 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -63,14 +63,14 @@ `define DTLB_ENTRIES 32 // Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_LINELENINBITS 256 `define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_BLOCKLENINBITS 256 +`define ICACHE_LINELENINBITS 256 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 64 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 6f7dbd886..7f8638e27 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -62,14 +62,14 @@ `define DTLB_ENTRIES 32 // Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_LINELENINBITS 256 `define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_BLOCKLENINBITS 256 +`define ICACHE_LINELENINBITS 256 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index b4b93ed03..4957a0e8c 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -62,14 +62,14 @@ `define DTLB_ENTRIES 32 // Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_BLOCKLENINBITS 256 +`define DCACHE_LINELENINBITS 256 `define DCACHE_REPLBITS 3 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_BLOCKLENINBITS 256 +`define ICACHE_LINELENINBITS 256 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 006a3e7c0..0bbafa6f2 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -176,182 +176,183 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED -add wave -noupdate -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState -add wave -noupdate -group lsu /testbench/dut/hart/lsu/SelHPTW -add wave -noupdate -group lsu /testbench/dut/hart/lsu/InterlockStall -add wave -noupdate -group lsu /testbench/dut/hart/lsu/LSUStall -add wave -noupdate -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM -add wave -noupdate -group lsu /testbench/dut/hart/lsu/ReadDataM -add wave -noupdate -group lsu /testbench/dut/hart/lsu/WriteDataM -add wave -noupdate -group lsu /testbench/dut/hart/lsu/SelUncachedAdr -add wave -noupdate -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/busfsm/BusCurrState -add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/BusStall -add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusRead -add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusWrite -add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAdr -add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAck -add wave -noupdate -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHWDATA -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/dcachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWriteEnableM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWayWriteEnableM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdrM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/RAdr -add wave -noupdate -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdr -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag -add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/RAdr -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WayHit} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/WayHit -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimTag -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuRWM -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAtomicM -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushDCacheM -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/DCacheStall -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM -add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit -add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheFetchLine -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheWriteLine -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAck -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/FlushWay -add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/StoreAccessFaultM -add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/AtomicAllowed -add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAStoreAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPStoreAccessFaultM -add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/WalkerState -add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF -add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE -add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr -add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE -add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF -add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM -add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF -add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/interlockfsm/InterlockCurrState +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataWordMuxM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/ReadDataM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelUncachedAdr +add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/hart/lsu/busfsm/BusCurrState +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/BusStall +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusRead +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusWrite +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAdr +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusAck +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/hart/lsu/LsuBusHWDATA +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcache/dcachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWayWriteEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMWordEnable +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SRAMBlockWayWriteEnableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/SelAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/MEM_VIRTMEM/SelReplayCPURequest +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/dcache/FlushAdrQ +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/hart/lsu/dcache/dcache/CacheableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WriteWordEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetValid} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/SetDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ClearDirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/VDWriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/WayHit} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/dcache/MemWay[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/dcache/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuRWM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAdrE +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuPAdrM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/LsuAtomicM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/CacheableM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/FlushDCacheM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/dcache/DCacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/FinalWriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/dcache/WayHit +add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheFetchLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheWriteLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheMemWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/dcache/DCacheBusAck +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/dmmu/StoreAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/AtomicAllowed +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/dmmu/PMAStoreAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/ReadAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/WriteAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/dmmu/PMPStoreAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/WalkerState +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PCF +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWReadPTE +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/PTE +add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBMissF +add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBMissM +add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/hart/lsu/MEM_VIRTMEM/hptw/DTLBWriteM add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR @@ -432,37 +433,30 @@ add wave -noupdate /testbench/dut/hart/lsu/LocalLsuBusAdr add wave -noupdate /testbench/dut/hart/lsu/busfsm/BusNextState add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheFetchLine add wave -noupdate /testbench/dut/hart/lsu/busfsm/DCacheWriteLine -add wave -noupdate -expand -group ifu -color Gold /testbench/dut/hart/ifu/busfsm/BusCurrState -add wave -noupdate -expand -group ifu /testbench/dut/hart/ifu/busfsm/LsuBusAck -add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/icache/icachefsm/CurrState -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/icachefsm/NextState -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/ITLBWriteF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/ReadLineF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/SelAdr -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCNextF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCPF -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCPSpillF -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/hit -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spill -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheStallF -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spillSave -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/spillSave -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/PreCntEn -add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/FinalInstrRawF -add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheBusAdr -add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheBusAck -add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheMemWriteEnable -add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheMemWriteData -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/ICacheMemReadData -add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/SpillDataBlock0 -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/TLBWrite -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/ITLBMissF -add wave -noupdate -expand -group ifu -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress +add wave -noupdate -group ifu -color Gold /testbench/dut/hart/ifu/busfsm/BusCurrState +add wave -noupdate -group ifu /testbench/dut/hart/ifu/busfsm/LsuBusAck +add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/icache/icachefsm/CurrState +add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/icachefsm/NextState +add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/ReadLineF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/SelAdr +add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCNextF +add wave -noupdate -group ifu -expand -group icache /testbench/dut/hart/ifu/icache/icache/PCPF +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/hit +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheStallF +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/icachefsm/PreCntEn +add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/icache/FinalInstrRawF +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheBusAdr +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheBusAck +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/icachefsm/ICacheMemWriteEnable +add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/icache/ICacheMemWriteData +add wave -noupdate -group ifu -group itlb /testbench/dut/hart/ifu/immu/TLBWrite +add wave -noupdate -group ifu -group itlb /testbench/dut/hart/ifu/ITLBMissF +add wave -noupdate -group ifu -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress add wave -noupdate /testbench/dut/hart/ifu/IfuBusRead add wave -noupdate /testbench/dut/hart/ifu/icache/icache/ICacheFetchLine TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {1239086 ns} 0} {{Cursor 4} {49574 ns} 1} +WaveRestoreCursors {{Cursor 7} {36865 ns} 1} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {38453 ns} 0} {{Cursor 4} {49574 ns} 1} quietly wave cursor active 3 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -478,4 +472,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {1238897 ns} {1239273 ns} +WaveRestoreZoom {38413 ns} {39039 ns} diff --git a/pipelined/src/cache/cachereplacementpolicy.sv b/pipelined/src/cache/cachereplacementpolicy.sv index 10e642a34..1ce84a320 100644 --- a/pipelined/src/cache/cachereplacementpolicy.sv +++ b/pipelined/src/cache/cachereplacementpolicy.sv @@ -40,7 +40,7 @@ module cachereplacementpolicy logic [NUMWAYS-2:0] LRUEn, LRUMask; logic [$clog2(NUMWAYS)-1:0] EncVicWay; logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0]; - logic [NUMWAYS-2:0] BlockReplacementBits; + logic [NUMWAYS-2:0] LineReplacementBits; logic [NUMWAYS-2:0] NewReplacement; logic [NUMWAYS-2:0] NewReplacementD; @@ -69,7 +69,7 @@ module cachereplacementpolicy end /* verilator lint_on BLKLOOPINIT */ - assign BlockReplacementBits = ReplacementBits[RAdrD]; + assign LineReplacementBits = ReplacementBits[RAdrD]; genvar index; generate @@ -79,16 +79,16 @@ module cachereplacementpolicy assign NewReplacement[0] = WayHit[1]; - assign VictimWay[1] = ~BlockReplacementBits[0]; - assign VictimWay[0] = BlockReplacementBits[0]; + assign VictimWay[1] = ~LineReplacementBits[0]; + assign VictimWay[0] = LineReplacementBits[0]; end else if (NUMWAYS == 4) begin : FourWay // VictimWay is a function only of the current value of the LRU. // binary encoding - //assign VictimWay[0] = BlockReplacementBits[2] ? BlockReplacementBits[1] : BlockReplacementBits[0]; - //assign VictimWay[1] = BlockReplacementBits[2]; + //assign VictimWay[0] = LineReplacementBits[2] ? LineReplacementBits[1] : LineReplacementBits[0]; + //assign VictimWay[1] = LineReplacementBits[2]; // 1 hot encoding //| WayHit | LRU 2 | LRU 1 | LRU 0 | @@ -99,10 +99,10 @@ module cachereplacementpolicy //| 0100 | 0 | 1 | - | //| 1000 | 0 | 0 | - | - assign VictimWay[0] = ~BlockReplacementBits[2] & ~BlockReplacementBits[0]; - assign VictimWay[1] = ~BlockReplacementBits[2] & BlockReplacementBits[0]; - assign VictimWay[2] = BlockReplacementBits[2] & ~BlockReplacementBits[1]; - assign VictimWay[3] = BlockReplacementBits[2] & BlockReplacementBits[1]; + assign VictimWay[0] = ~LineReplacementBits[2] & ~LineReplacementBits[0]; + assign VictimWay[1] = ~LineReplacementBits[2] & LineReplacementBits[0]; + assign VictimWay[2] = LineReplacementBits[2] & ~LineReplacementBits[1]; + assign VictimWay[3] = LineReplacementBits[2] & LineReplacementBits[1]; // New LRU bits which are updated is function only of the WayHit. // However the not updated bits come from the old LRU. @@ -128,11 +128,11 @@ module cachereplacementpolicy -----/\----- EXCLUDED -----/\----- */ for(index = 0; index < NUMWAYS-1; index++) - assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : BlockReplacementBits[index]; + assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index]; /* -----\/----- EXCLUDED -----\/----- - assign EncVicWay[1] = BlockReplacementBits[2]; - assign EncVicWay[0] = BlockReplacementBits[2] ? BlockReplacementBits[0] : BlockReplacementBits[1]; + assign EncVicWay[1] = LineReplacementBits[2]; + assign EncVicWay[0] = LineReplacementBits[2] ? LineReplacementBits[0] : LineReplacementBits[1]; onehotdecoder #(2) waydec(.bin(EncVicWay), @@ -160,12 +160,12 @@ module cachereplacementpolicy assign LRUMask[0] = WayHit[0]; for(index = 0; index < NUMWAYS-1; index++) - assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : BlockReplacementBits[index]; + assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index]; - assign EncVicWay[2] = BlockReplacementBits[6]; - assign EncVicWay[1] = BlockReplacementBits[6] ? BlockReplacementBits[5] : BlockReplacementBits[2]; - assign EncVicWay[0] = BlockReplacementBits[6] ? BlockReplacementBits[5] ? BlockReplacementBits[4] : BlockReplacementBits[3] : - BlockReplacementBits[2] ? BlockReplacementBits[1] : BlockReplacementBits[0]; + assign EncVicWay[2] = LineReplacementBits[6]; + assign EncVicWay[1] = LineReplacementBits[6] ? LineReplacementBits[5] : LineReplacementBits[2]; + assign EncVicWay[0] = LineReplacementBits[6] ? LineReplacementBits[5] ? LineReplacementBits[4] : LineReplacementBits[3] : + LineReplacementBits[2] ? LineReplacementBits[1] : LineReplacementBits[0]; onehotdecoder #(3) diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 158b6252c..ce25ab862 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -25,7 +25,7 @@ `include "wally-config.vh" -module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, +module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) (input logic clk, input logic reset, @@ -34,9 +34,9 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, input logic [`PA_BITS-1:0] PAdr, input logic WriteEnable, input logic VDWriteEnable, - input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable, + input logic [LINELEN/`XLEN-1:0] WriteWordEnable, input logic TagWriteEnable, - input logic [BLOCKLEN-1:0] WriteData, + input logic [LINELEN-1:0] WriteData, input logic SetValid, input logic ClearValid, input logic SetDirty, @@ -47,7 +47,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, input logic SelFlush, input logic FlushWay, - output logic [BLOCKLEN-1:0] ReadDataLineWayMasked, + output logic [LINELEN-1:0] ReadDataLineWayMasked, output logic WayHit, output logic VictimDirtyWay, output logic [TAGLEN-1:0] VictimTagWay @@ -55,7 +55,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, logic [NUMLINES-1:0] ValidBits; logic [NUMLINES-1:0] DirtyBits; - logic [BLOCKLEN-1:0] ReadDataBlockWay; + logic [LINELEN-1:0] ReadDataLineWay; logic [TAGLEN-1:0] ReadTag; logic Valid; logic Dirty; @@ -74,10 +74,10 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, genvar words; generate - for(words = 0; words < BLOCKLEN/`XLEN; words++) begin : word + for(words = 0; words < LINELEN/`XLEN; words++) begin : word sram1rw #(.DEPTH(`XLEN), .WIDTH(NUMLINES)) CacheDataMem(.clk(clk), .Addr(RAdr), - .ReadData(ReadDataBlockWay[(words+1)*`XLEN-1:words*`XLEN] ), + .ReadData(ReadDataLineWay[(words+1)*`XLEN-1:words*`XLEN] ), .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]), .WriteEnable(WriteEnable & WriteWordEnable[words])); end @@ -93,7 +93,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); assign SelectedWay = SelFlush ? FlushWay : SelEvict ? VictimWay : WayHit; - assign ReadDataLineWayMasked = SelectedWay ? ReadDataBlockWay : '0; // first part of AO mux. + assign ReadDataLineWayMasked = SelectedWay ? ReadDataLineWay : '0; // first part of AO mux. assign VictimDirtyWay = SelFlush ? FlushWay & Dirty & Valid : VictimWay & Dirty & Valid; diff --git a/pipelined/src/cache/dcache.sv b/pipelined/src/cache/dcache.sv index caaaa7169..d2c471697 100644 --- a/pipelined/src/cache/dcache.sv +++ b/pipelined/src/cache/dcache.sv @@ -52,8 +52,8 @@ module dcache output logic [`PA_BITS-1:0] DCacheBusAdr, - input logic [`DCACHE_BLOCKLENINBITS-1:0] DCacheMemWriteData, - output logic [`XLEN-1:0] ReadDataBlockSetsM [(`DCACHE_BLOCKLENINBITS/`XLEN)-1:0], + input logic [`DCACHE_LINELENINBITS-1:0] DCacheMemWriteData, + output logic [`XLEN-1:0] ReadDataLineSetsM [(`DCACHE_LINELENINBITS/`XLEN)-1:0], output logic DCacheStall, @@ -62,15 +62,15 @@ module dcache output logic DCacheAccess ); - localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS; - localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/BLOCKLEN; + localparam integer LINELEN = `DCACHE_LINELENINBITS; + localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/LINELEN; localparam integer NUMWAYS = `DCACHE_NUMWAYS; - localparam integer BLOCKBYTELEN = BLOCKLEN/8; - localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); + localparam integer LINEBYTELEN = LINELEN/8; + localparam integer OFFSETLEN = $clog2(LINEBYTELEN); localparam integer INDEXLEN = $clog2(NUMLINES); localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; - localparam integer WORDSPERLINE = BLOCKLEN/`XLEN; + localparam integer WORDSPERLINE = LINELEN/`XLEN; localparam integer LOGWPL = $clog2(WORDSPERLINE); localparam integer LOGXLENBYTES = $clog2(`XLEN/8); @@ -78,18 +78,18 @@ module dcache logic [1:0] SelAdrM; logic [INDEXLEN-1:0] RAdr; - logic [BLOCKLEN-1:0] SRAMWriteData; + logic [LINELEN-1:0] SRAMWriteData; logic SetValid, ClearValid; logic SetDirty, ClearDirty; - logic [BLOCKLEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0]; + logic [LINELEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0]; logic [NUMWAYS-1:0] WayHit; logic CacheHit; - logic [BLOCKLEN-1:0] ReadDataLineM; + logic [LINELEN-1:0] ReadDataLineM; logic [WORDSPERLINE-1:0] SRAMWordEnable; logic SRAMWordWriteEnableM; - logic SRAMBlockWriteEnableM; - logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM; + logic SRAMLineWriteEnableM; + logic [NUMWAYS-1:0] SRAMLineWayWriteEnableM; logic [NUMWAYS-1:0] SRAMWayWriteEnable; @@ -129,14 +129,14 @@ module dcache .s(SelAdrM), .y(RAdr)); - cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), + cacheway #(.NUMLINES(NUMLINES), .LINELEN(LINELEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN)) MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr, .PAdr(LsuPAdrM), .WriteEnable(SRAMWayWriteEnable), .VDWriteEnable(VDWriteEnableWay), .WriteWordEnable(SRAMWordEnable), - .TagWriteEnable(SRAMBlockWayWriteEnableM), + .TagWriteEnable(SRAMLineWayWriteEnableM), .WriteData(SRAMWriteData), .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SelEvict, .VictimWay, .FlushWay, .SelFlush, @@ -162,10 +162,10 @@ module dcache assign VictimDirty = | VictimDirtyWay; - // ReadDataLineWayMaskedM is a 2d array of cache block len by number of ways. + // ReadDataLineWayMaskedM is a 2d array of cache line len by number of ways. // Need to OR together each way in a bitwise manner. // Final part of the AO Mux. First is the AND in the cacheway. - or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLineM)); + or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadDataLineM)); or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag)); @@ -174,14 +174,14 @@ module dcache // *** consider using a limited range shift to do this final muxing. genvar index; generate - for (index = 0; index < WORDSPERLINE; index++) begin:readdatablocksetsmux - assign ReadDataBlockSetsM[index] = ReadDataLineM[((index+1)*`XLEN)-1: (index*`XLEN)]; + for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux + assign ReadDataLineSetsM[index] = ReadDataLineM[((index+1)*`XLEN)-1: (index*`XLEN)]; end endgenerate // variable input mux - assign ReadDataWordM = ReadDataBlockSetsM[LsuPAdrM[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]]; + assign ReadDataWordM = ReadDataLineSetsM[LsuPAdrM[LOGWPL + LOGXLENBYTES - 1 : LOGXLENBYTES]]; // Write Path CPU (IEU) side @@ -189,20 +189,20 @@ module dcache adrdec(.bin(LsuPAdrM[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecodedW)); - assign SRAMWordEnable = SRAMBlockWriteEnableM ? '1 : MemPAdrDecodedW; + assign SRAMWordEnable = SRAMLineWriteEnableM ? '1 : MemPAdrDecodedW; - assign SRAMBlockWayWriteEnableM = SRAMBlockWriteEnableM ? VictimWay : '0; + assign SRAMLineWayWriteEnableM = SRAMLineWriteEnableM ? VictimWay : '0; mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableM ? WayHit : '0), - .d1(SRAMBlockWayWriteEnableM), - .s(SRAMBlockWriteEnableM), + .d1(SRAMLineWayWriteEnableM), + .s(SRAMLineWriteEnableM), .y(SRAMWayWriteEnable)); - mux2 #(BLOCKLEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteDataM}}), + mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteDataM}}), .d1(DCacheMemWriteData), - .s(SRAMBlockWriteEnableM), + .s(SRAMLineWriteEnableM), .y(SRAMWriteData)); @@ -251,7 +251,7 @@ module dcache .CacheHit, .VictimDirty, .DCacheStall, .DCacheCommittedM, .DCacheMiss, .DCacheAccess, .SelAdrM, .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM, - .SRAMBlockWriteEnableM, .SelEvict, .SelFlush, + .SRAMLineWriteEnableM, .SelEvict, .SelFlush, .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, .FlushWayCntRst, .FlushAdrFlag, .FlushDCacheM, .VDWriteEnable, .LRUWriteEn); diff --git a/pipelined/src/cache/dcachefsm.sv b/pipelined/src/cache/dcachefsm.sv index 4069eae22..6e1e53b57 100644 --- a/pipelined/src/cache/dcachefsm.sv +++ b/pipelined/src/cache/dcachefsm.sv @@ -61,7 +61,7 @@ module dcachefsm output logic SetDirty, output logic ClearDirty, output logic SRAMWordWriteEnableM, - output logic SRAMBlockWriteEnableM, + output logic SRAMLineWriteEnableM, output logic SelEvict, output logic LRUWriteEn, output logic SelFlush, @@ -80,7 +80,7 @@ module dcachefsm STATE_MISS_FETCH_WDV, STATE_MISS_FETCH_DONE, STATE_MISS_EVICT_DIRTY, - STATE_MISS_WRITE_CACHE_BLOCK, + STATE_MISS_WRITE_CACHE_LINE, STATE_MISS_READ_WORD, STATE_MISS_READ_WORD_DELAY, STATE_MISS_WRITE_WORD, @@ -113,7 +113,7 @@ module dcachefsm SetDirty = 1'b0; ClearDirty = 1'b0; SRAMWordWriteEnableM = 1'b0; - SRAMBlockWriteEnableM = 1'b0; + SRAMLineWriteEnableM = 1'b0; SelEvict = 1'b0; LRUWriteEn = 1'b0; SelFlush = 1'b0; @@ -228,12 +228,12 @@ module dcachefsm NextState = STATE_MISS_EVICT_DIRTY; DCacheWriteLine = 1'b1; end else begin - NextState = STATE_MISS_WRITE_CACHE_BLOCK; + NextState = STATE_MISS_WRITE_CACHE_LINE; end end - STATE_MISS_WRITE_CACHE_BLOCK: begin - SRAMBlockWriteEnableM = 1'b1; + STATE_MISS_WRITE_CACHE_LINE: begin + SRAMLineWriteEnableM = 1'b1; DCacheStall = 1'b1; NextState = STATE_MISS_READ_WORD; SelAdrM = 2'b01; @@ -301,7 +301,7 @@ module dcachefsm SelAdrM = 2'b01; SelEvict = 1'b1; if(DCacheBusAck) begin - NextState = STATE_MISS_WRITE_CACHE_BLOCK; + NextState = STATE_MISS_WRITE_CACHE_LINE; end else begin NextState = STATE_MISS_EVICT_DIRTY; end diff --git a/pipelined/src/cache/icache.sv b/pipelined/src/cache/icache.sv index b54accf57..f6ad7484c 100644 --- a/pipelined/src/cache/icache.sv +++ b/pipelined/src/cache/icache.sv @@ -43,7 +43,7 @@ module icache // bus fsm interface input logic IgnoreRequest, - input logic [`ICACHE_BLOCKLENINBITS-1:0] ICacheMemWriteData, + input logic [`ICACHE_LINELENINBITS-1:0] ICacheMemWriteData, output logic ICacheFetchLine, (* mark_debug = "true" *) input logic ICacheBusAck, @@ -57,16 +57,16 @@ module icache ); // Configuration parameters - localparam integer BLOCKLEN = `ICACHE_BLOCKLENINBITS; - localparam integer NUMLINES = `ICACHE_WAYSIZEINBYTES*8/`ICACHE_BLOCKLENINBITS; - localparam integer BLOCKBYTELEN = BLOCKLEN/8; + localparam integer LINELEN = `ICACHE_LINELENINBITS; + localparam integer NUMLINES = `ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS; + localparam integer LINEBYTELEN = LINELEN/8; - localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); + localparam integer OFFSETLEN = $clog2(LINEBYTELEN); localparam integer INDEXLEN = $clog2(NUMLINES); localparam integer TAGLEN = `PA_BITS - OFFSETLEN - INDEXLEN; // *** not used? - localparam WORDSPERLINE = BLOCKLEN/`XLEN; + localparam WORDSPERLINE = LINELEN/`XLEN; localparam LOGWPL = $clog2(WORDSPERLINE); localparam integer NUMWAYS = `ICACHE_NUMWAYS; @@ -75,7 +75,7 @@ module icache // Input signals to cache memory logic ICacheMemWriteEnable; // Output signals from cache memory - logic [BLOCKLEN-1:0] ReadLineF; + logic [LINELEN-1:0] ReadLineF; logic SelAdr; logic [INDEXLEN-1:0] RAdr; logic [NUMWAYS-1:0] VictimWay; @@ -84,9 +84,9 @@ module icache logic hit; - logic [BLOCKLEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0]; + logic [LINELEN-1:0] ReadDataLineWayMasked [NUMWAYS-1:0]; - logic [31:0] ReadLineSetsF [`ICACHE_BLOCKLENINBITS/16-1:0]; + logic [31:0] ReadLineSetsF [`ICACHE_LINELENINBITS/16-1:0]; logic [NUMWAYS-1:0] SRAMWayWriteEnable; @@ -98,13 +98,13 @@ module icache .y(RAdr)); - cacheway #(.NUMLINES(NUMLINES), .BLOCKLEN(BLOCKLEN), .TAGLEN(TAGLEN), + cacheway #(.NUMLINES(NUMLINES), .LINELEN(LINELEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN), .DIRTY_BITS(0)) MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr, .PAdr(PCPF), .WriteEnable(SRAMWayWriteEnable), .VDWriteEnable(1'b0), - .WriteWordEnable({{(BLOCKLEN/`XLEN){1'b1}}}), + .WriteWordEnable({{(LINELEN/`XLEN){1'b1}}}), .TagWriteEnable(SRAMWayWriteEnable), .WriteData(ICacheMemWriteData), .SetValid(ICacheMemWriteEnable), @@ -131,20 +131,20 @@ module icache assign hit = | WayHit; - // ReadDataLineWayMasked is a 2d array of cache block len by number of ways. + // ReadDataLineWayMasked is a 2d array of cache line len by number of ways. // Need to OR together each way in a bitwise manner. // Final part of the AO Mux. First is the AND in the cacheway. - or_rows #(NUMWAYS, BLOCKLEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadLineF)); + or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWayMasked), .y(ReadLineF)); genvar index; generate - for(index = 0; index < BLOCKLEN / 16 - 1; index++) begin:readlinesetsmux + for(index = 0; index < LINELEN / 16 - 1; index++) begin:readlinesetsmux assign ReadLineSetsF[index] = ReadLineF[((index+1)*16)+16-1 : (index*16)]; end - assign ReadLineSetsF[BLOCKLEN/16-1] = {16'b0, ReadLineF[BLOCKLEN-1:BLOCKLEN-16]}; + assign ReadLineSetsF[LINELEN/16-1] = {16'b0, ReadLineF[LINELEN-1:LINELEN-16]}; endgenerate - assign FinalInstrRawF = ReadLineSetsF[PCPF[$clog2(BLOCKLEN / 32) + 1 : 1]]; + assign FinalInstrRawF = ReadLineSetsF[PCPF[$clog2(LINELEN / 32) + 1 : 1]]; assign ICacheBusAdr = {PCPF[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}; diff --git a/pipelined/src/cache/icachefsm.sv b/pipelined/src/cache/icachefsm.sv index ead8afd84..aea8a7377 100644 --- a/pipelined/src/cache/icachefsm.sv +++ b/pipelined/src/cache/icachefsm.sv @@ -59,8 +59,8 @@ module icachefsm STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data. STATE_MISS_FETCH_DONE, // write data into SRAM/LUT - STATE_MISS_READ, // read block 1 from SRAM/LUT - STATE_MISS_READ_DELAY, // read block 1 from SRAM/LUT + STATE_MISS_READ, // read line 1 from SRAM/LUT + STATE_MISS_READ_DELAY, // read line 1 from SRAM/LUT STATE_CPU_BUSY } statetype; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 8a0c36d75..8d963176f 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -116,7 +116,7 @@ module ifu ( logic [`XLEN-1:0] PCFp2; logic Spill; logic SelSpill, SpillSave; - logic [15:0] SpillDataBlock0; + logic [15:0] SpillDataLine0; // this exists only if there are compressed instructions. assign PCFp2 = PCF + `XLEN'b10; @@ -124,7 +124,7 @@ module ifu ( assign PCNextFMux = SelNextSpill ? PCFp2[11:0] : PCNextF[11:0]; assign PCFMux = SelSpill ? PCFp2 : PCF; - assign Spill = &PCF[$clog2(`ICACHE_BLOCKLENINBITS/32)+1:1]; + assign Spill = &PCF[$clog2(`ICACHE_LINELENINBITS/32)+1:1]; typedef enum {STATE_SPILL_READY, STATE_SPILL_SPILL} statetype; (* mark_debug = "true" *) statetype CurrState, NextState; @@ -154,13 +154,13 @@ module ifu ( .en(SpillSave), .reset(reset), .d(InstrRawF[15:0]), - .q(SpillDataBlock0)); + .q(SpillDataLine0)); - assign PostSpillInstrRawF = Spill ? {InstrRawF[15:0], SpillDataBlock0} : InstrRawF; + assign PostSpillInstrRawF = Spill ? {InstrRawF[15:0], SpillDataLine0} : InstrRawF; assign CompressedF = PostSpillInstrRawF[1:0] != 2'b11; // end of spill support - end else begin : NoSpillSupport // block: SpillSupport + end else begin : NoSpillSupport // line: SpillSupport assign PCNextFMux = PCNextF[11:0]; assign PCFMux = PCF; assign SelNextSpill = 0; @@ -220,16 +220,16 @@ module ifu ( // 2. cache // `MEM_ICACHE // 3. wire pass-through - localparam integer WORDSPERLINE = `MEM_ICACHE ? `ICACHE_BLOCKLENINBITS/`XLEN : 1; + localparam integer WORDSPERLINE = `MEM_ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam integer LOGWPL = `MEM_ICACHE ? $clog2(WORDSPERLINE) : 1; - localparam integer BLOCKLEN = `MEM_ICACHE ? `ICACHE_BLOCKLENINBITS : `XLEN; + localparam integer LINELEN = `MEM_ICACHE ? `ICACHE_LINELENINBITS : `XLEN; localparam integer WordCountThreshold = `MEM_ICACHE ? WORDSPERLINE - 1 : 0; - localparam integer BLOCKBYTELEN = BLOCKLEN/8; - localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); + localparam integer LINEBYTELEN = LINELEN/8; + localparam integer OFFSETLEN = $clog2(LINEBYTELEN); logic [LOGWPL-1:0] WordCount; - logic [BLOCKLEN-1:0] ICacheMemWriteData; + logic [LINELEN-1:0] ICacheMemWriteData; logic ICacheBusAck; logic [`PA_BITS-1:0] LocalIfuBusAdr; logic [`PA_BITS-1:0] ICacheBusAdr; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 2575774a6..876c2d898 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -273,20 +273,20 @@ module lsu // 2. cache `MEM_DCACHE // 3. wire pass-through - localparam integer WORDSPERLINE = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS/`XLEN : 1; + localparam integer WORDSPERLINE = `MEM_DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1; localparam integer LOGWPL = `MEM_DCACHE ? $clog2(WORDSPERLINE) : 1; - localparam integer BLOCKLEN = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS : `XLEN; + localparam integer LINELEN = `MEM_DCACHE ? `DCACHE_LINELENINBITS : `XLEN; localparam integer WordCountThreshold = `MEM_DCACHE ? WORDSPERLINE - 1 : 0; - localparam integer BLOCKBYTELEN = BLOCKLEN/8; - localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); + localparam integer LINEBYTELEN = LINELEN/8; + localparam integer OFFSETLEN = $clog2(LINEBYTELEN); // temp logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM; (* mark_debug = "true" *) logic [`XLEN-1:0] PreLsuBusHWDATA; logic [`XLEN-1:0] ReadDataWordM; - logic [BLOCKLEN-1:0] DCacheMemWriteData; + logic [LINELEN-1:0] DCacheMemWriteData; // keep logic [`XLEN-1:0] ReadDataWordMuxM; @@ -294,7 +294,7 @@ module lsu logic [`PA_BITS-1:0] DCacheBusAdr; - logic [`XLEN-1:0] ReadDataBlockSetsM [WORDSPERLINE-1:0]; + logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0]; @@ -311,7 +311,7 @@ module lsu .FinalWriteDataM, .ReadDataWordM, .DCacheStall, .DCacheMiss, .DCacheAccess, .IgnoreRequest, .CacheableM, .DCacheCommittedM, - .DCacheBusAdr, .ReadDataBlockSetsM, .DCacheMemWriteData, + .DCacheBusAdr, .ReadDataLineSetsM, .DCacheMemWriteData, .DCacheFetchLine, .DCacheWriteLine,.DCacheBusAck); end else begin : passthrough assign ReadDataWordM = 0; @@ -322,7 +322,7 @@ module lsu assign DCacheWriteLine = 0; assign DCacheFetchLine = 0; assign DCacheBusAdr = 0; - assign ReadDataBlockSetsM[0] = 0; + assign ReadDataLineSetsM[0] = 0; end endgenerate @@ -376,7 +376,7 @@ module lsu assign LocalLsuBusAdr = SelUncachedAdr ? LsuPAdrM : DCacheBusAdr ; assign LsuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLsuBusAdr; - assign PreLsuBusHWDATA = ReadDataBlockSetsM[WordCount]; + assign PreLsuBusHWDATA = ReadDataLineSetsM[WordCount]; assign LsuBusHWDATA = SelUncachedAdr ? WriteDataM : PreLsuBusHWDATA; // *** why is this not FinalWriteDataM? which does not work. generate diff --git a/pipelined/testbench/testbench-fpga.sv b/pipelined/testbench/testbench-fpga.sv index 15840b27b..9c15f1668 100644 --- a/pipelined/testbench/testbench-fpga.sv +++ b/pipelined/testbench/testbench-fpga.sv @@ -783,14 +783,14 @@ module riscvassertions(); assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double without supporting float"); assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32"); assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`DCACHE_BLOCKLENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled"); - assert (`DCACHE_BLOCKLENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_BLOCKLENINBITS must be smaller than way size"); + assert (`DCACHE_LINELENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_BLOCKLENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled"); - assert (`ICACHE_BLOCKLENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_BLOCKLENINBITS must be smaller than way size"); - assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS) else $error("DCACHE_BLOCKLENINBITS must be a power of 2"); + assert (`ICACHE_LINELENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); + assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); + assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS) else $error("DCACHE_LINELENINBITS must be a power of 2"); assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS) else $error("ICACHE_BLOCKLENINBITS must be a power of 2"); + assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS) else $error("ICACHE_LINELENINBITS must be a power of 2"); assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); assert (`ICACHE_NUMWAYS == 1 | `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented"); assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2"); @@ -811,12 +811,12 @@ module DCacheFlushFSM localparam integer numlines = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.NUMLINES; localparam integer numways = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.NUMWAYS; - localparam integer blockbytelen = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.BLOCKBYTELEN; - localparam integer numwords = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.BLOCKLEN/`XLEN; + localparam integer linebytelen = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.LINEBYTELEN; + localparam integer numwords = testbench.dut.wallypipelinedsoc.hart.lsu.dcache.LINELEN/`XLEN; localparam integer lognumlines = $clog2(numlines); - localparam integer logblockbytelen = $clog2(blockbytelen); + localparam integer loglinebytelen = $clog2(linebytelen); localparam integer lognumways = $clog2(numways); - localparam integer tagstart = lognumlines + logblockbytelen; + localparam integer tagstart = lognumlines + loglinebytelen; @@ -835,7 +835,7 @@ module DCacheFlushFSM for(way = 0; way < numways; way++) begin for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin copyShadow #(.tagstart(tagstart), - .logblockbytelen(logblockbytelen)) + .loglinebytelen(loglinebytelen)) copyShadow(.clk, .start, .tag(testbench.dut.wallypipelinedsoc.hart.lsu.dcache.MemWay[way].CacheTagMem.StoredData[index]), @@ -879,7 +879,7 @@ module DCacheFlushFSM endmodule module copyShadow - #(parameter tagstart, logblockbytelen) + #(parameter tagstart, loglinebytelen) (input logic clk, input logic start, input logic [`PA_BITS-1:tagstart] tag, @@ -900,7 +900,7 @@ module copyShadow CacheValid = valid; CacheDirty = dirty; CacheData = data; - CacheAdr = (tag << tagstart) + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8)); + CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8)); end end diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index bbb0df15d..e67e649d7 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -338,14 +338,14 @@ module riscvassertions; assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)"); assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32"); assert (`DCACHE_WAYSIZEINBYTES <= 4096 | `MEM_DCACHE == 0 | `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`DCACHE_BLOCKLENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled"); - assert (`DCACHE_BLOCKLENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_BLOCKLENINBITS must be smaller than way size"); + assert (`DCACHE_LINELENINBITS >= 128 | `MEM_DCACHE == 0) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); assert (`ICACHE_WAYSIZEINBYTES <= 4096 | `MEM_ICACHE == 0 | `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_BLOCKLENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled"); - assert (`ICACHE_BLOCKLENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_BLOCKLENINBITS must be smaller than way size"); - assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS | `MEM_DCACHE==0) else $error("DCACHE_BLOCKLENINBITS must be a power of 2"); + assert (`ICACHE_LINELENINBITS >= 32 | `MEM_ICACHE == 0) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); + assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); + assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | `MEM_DCACHE==0) else $error("DCACHE_LINELENINBITS must be a power of 2"); assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | `MEM_DCACHE==0) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS | `MEM_ICACHE==0) else $error("ICACHE_BLOCKLENINBITS must be a power of 2"); + assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | `MEM_ICACHE==0) else $error("ICACHE_LINELENINBITS must be a power of 2"); assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | `MEM_ICACHE==0) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `MEM_VIRTMEM==0) else $error("ITLB_ENTRIES must be a power of 2"); assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `MEM_VIRTMEM==0) else $error("DTLB_ENTRIES must be a power of 2"); @@ -374,12 +374,12 @@ module DCacheFlushFSM if(`MEM_DCACHE) begin localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES; localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS; - localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.dcache.BLOCKBYTELEN; - localparam integer numwords = testbench.dut.hart.lsu.dcache.dcache.BLOCKLEN/`XLEN; + localparam integer linebytelen = testbench.dut.hart.lsu.dcache.dcache.LINEBYTELEN; + localparam integer numwords = testbench.dut.hart.lsu.dcache.dcache.LINELEN/`XLEN; localparam integer lognumlines = $clog2(numlines); - localparam integer logblockbytelen = $clog2(blockbytelen); + localparam integer loglinebytelen = $clog2(linebytelen); localparam integer lognumways = $clog2(numways); - localparam integer tagstart = lognumlines + logblockbytelen; + localparam integer tagstart = lognumlines + loglinebytelen; @@ -393,7 +393,7 @@ module DCacheFlushFSM for(way = 0; way < numways; way++) begin for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin copyShadow #(.tagstart(tagstart), - .logblockbytelen(logblockbytelen)) + .loglinebytelen(loglinebytelen)) copyShadow(.clk, .start, .tag(testbench.dut.hart.lsu.dcache.dcache.MemWay[way].CacheTagMem.StoredData[index]), @@ -442,7 +442,7 @@ module DCacheFlushFSM endmodule module copyShadow - #(parameter tagstart, logblockbytelen) + #(parameter tagstart, loglinebytelen) (input logic clk, input logic start, input logic [`PA_BITS-1:tagstart] tag, @@ -463,7 +463,7 @@ module copyShadow CacheValid = valid; CacheDirty = dirty; CacheData = data; - CacheAdr = (tag << tagstart) + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8)); + CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8)); end end