Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

pipelined/regression/regression-wally

@@ -91,6 +91,16 @@ for test in tests32ic:
         grepstr="All tests ran without failures")
   configs.append(tc)
 
+tests32i = ["wally32periph"] 
+for test in tests32i:
+  tc = TestCase(
+        name=test,
+        variant="rv32i",
+        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32i "+test+"\n!",
+        grepstr="All tests ran without failures")
+  configs.append(tc)
+
+
 tests32e = ["wally32e"] 
 for test in tests32e:
   tc = TestCase(

pipelined/src/fpu/fdivsqrt.sv

@@ -61,17 +61,16 @@ module fdivsqrt(
   logic [`DIVN-2:0] Dpreproc;
   logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM;
   logic [`DIVb-1:0] FirstC;
-  logic [`DURLEN-1:0] Dur;
   logic NegSticky;
   logic [`DIVCOPIES-1:0] qn;
   logic WZero;
 
   fdivsqrtpreproc fdivsqrtpreproc(
     .clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), 
-    .Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc);
+    .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc);
   fdivsqrtfsm fdivsqrtfsm(
     .reset, .XsE, .SqrtE, 
-    .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, 
+    .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, 
     .XNaNE, .YNaNE,
     .XInfE, .YInfE, .EarlyTermShiftE(EarlyTermShiftM), .WZero);
   fdivsqrtiter fdivsqrtiter(

pipelined/src/fpu/fdivsqrtfsm.sv

@@ -41,7 +41,6 @@ module fdivsqrtfsm(
   input  logic SqrtE,
   input  logic StallE,
   input  logic StallM,
-  input  logic [`DURLEN-1:0] Dur,
   input logic WZero,
   output logic [`DURLEN-1:0] EarlyTermShiftE,
   output logic DivDone,
@@ -63,7 +62,7 @@ module fdivsqrtfsm(
       if (reset) begin
           state <= #1 IDLE; 
       end else if (DivStart&~StallE) begin 
-          step <= Dur;
+          step <= (`DURLEN)'(`FPDUR); // *** this should be adjusted to depend on the precision
           if (SpecialCase) state <= #1 DONE;
           else             state <= #1 BUSY;
       end else if (DivDone) begin

pipelined/src/fpu/fdivsqrtpreproc.sv

@@ -40,8 +40,7 @@ module fdivsqrtpreproc (
   input logic XZero,
   output logic  [`NE+1:0] QeM,
   output logic [`DIVb:0] X,
-  output logic [`DIVN-2:0] Dpreproc,
+  output logic [`DIVN-2:0] Dpreproc
-  output logic [`DURLEN-1:0] Dur
 );
   // logic  [`XLEN-1:0] PosA, PosB;
   // logic  [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY;
@@ -73,7 +72,6 @@ module fdivsqrtpreproc (
   assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0};
   assign X = Sqrt ? {SqrtX, {`DIVb-1-`NF{1'b0}}} : {~XZero, PreprocX, {`DIVb-`NF{1'b0}}};
   assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}};
-  assign Dur = (`DURLEN)'(`FPDUR);
 
   //           radix 2     radix 4
   // 1 copies  DIVLEN+2    DIVLEN+2/2

pipelined/testbench/testbench-fp.sv

@@ -585,7 +585,7 @@ module testbenchfp;
       end
       if (TEST === "sqrt"  | TEST === "all") begin // if sqrt is being tested
         // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {Tests, f16sqrt};
+        Tests = {f16sqrt, Tests};
         OpCtrl = {OpCtrl, `SQRT_OPCTRL};
         WriteInt = {WriteInt, 1'b0};
         for(int i = 0; i<5; i++) begin