diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index 041803167..63c0c5073 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -618,3 +618,14 @@ create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe131]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe131]
 connect_debug_port u_ila_0/probe131 [get_nets [list {wallypipelinedsoc/hart/priv.priv/CSRWriteM} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe132]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe132]
+connect_debug_port u_ila_0/probe132 [get_nets [list {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[0]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[1]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[2]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[3]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[4]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[5]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[6]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[7]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[8]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[9]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[10]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[11]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[12]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[13]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[14]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[15]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[16]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[17]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[18]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[19]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[20]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[21]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[22]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[23]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[24]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[25]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[26]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[27]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[28]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[29]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[30]} {wallypipelinedsoc/hart/ifu/PostSpillInstrRawF[31]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe133]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133]
+connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/hart/ifu/PCNextF[0]} {wallypipelinedsoc/hart/ifu/PCNextF[1]} {wallypipelinedsoc/hart/ifu/PCNextF[2]} {wallypipelinedsoc/hart/ifu/PCNextF[3]} {wallypipelinedsoc/hart/ifu/PCNextF[4]} {wallypipelinedsoc/hart/ifu/PCNextF[5]} {wallypipelinedsoc/hart/ifu/PCNextF[6]} {wallypipelinedsoc/hart/ifu/PCNextF[7]} {wallypipelinedsoc/hart/ifu/PCNextF[8]} {wallypipelinedsoc/hart/ifu/PCNextF[9]} {wallypipelinedsoc/hart/ifu/PCNextF[10]} {wallypipelinedsoc/hart/ifu/PCNextF[11]} {wallypipelinedsoc/hart/ifu/PCNextF[12]} {wallypipelinedsoc/hart/ifu/PCNextF[13]} {wallypipelinedsoc/hart/ifu/PCNextF[14]} {wallypipelinedsoc/hart/ifu/PCNextF[15]} {wallypipelinedsoc/hart/ifu/PCNextF[16]} {wallypipelinedsoc/hart/ifu/PCNextF[17]} {wallypipelinedsoc/hart/ifu/PCNextF[18]} {wallypipelinedsoc/hart/ifu/PCNextF[19]} {wallypipelinedsoc/hart/ifu/PCNextF[20]} {wallypipelinedsoc/hart/ifu/PCNextF[21]} {wallypipelinedsoc/hart/ifu/PCNextF[22]} {wallypipelinedsoc/hart/ifu/PCNextF[23]} {wallypipelinedsoc/hart/ifu/PCNextF[24]} {wallypipelinedsoc/hart/ifu/PCNextF[25]} {wallypipelinedsoc/hart/ifu/PCNextF[26]} {wallypipelinedsoc/hart/ifu/PCNextF[27]} {wallypipelinedsoc/hart/ifu/PCNextF[28]} {wallypipelinedsoc/hart/ifu/PCNextF[29]} {wallypipelinedsoc/hart/ifu/PCNextF[30]} {wallypipelinedsoc/hart/ifu/PCNextF[31]} {wallypipelinedsoc/hart/ifu/PCNextF[32]} {wallypipelinedsoc/hart/ifu/PCNextF[33]} {wallypipelinedsoc/hart/ifu/PCNextF[34]} {wallypipelinedsoc/hart/ifu/PCNextF[35]} {wallypipelinedsoc/hart/ifu/PCNextF[36]} {wallypipelinedsoc/hart/ifu/PCNextF[37]} {wallypipelinedsoc/hart/ifu/PCNextF[38]} {wallypipelinedsoc/hart/ifu/PCNextF[39]} {wallypipelinedsoc/hart/ifu/PCNextF[40]} {wallypipelinedsoc/hart/ifu/PCNextF[41]} {wallypipelinedsoc/hart/ifu/PCNextF[42]} {wallypipelinedsoc/hart/ifu/PCNextF[43]} {wallypipelinedsoc/hart/ifu/PCNextF[44]} {wallypipelinedsoc/hart/ifu/PCNextF[45]} {wallypipelinedsoc/hart/ifu/PCNextF[46]} {wallypipelinedsoc/hart/ifu/PCNextF[47]} {wallypipelinedsoc/hart/ifu/PCNextF[48]} {wallypipelinedsoc/hart/ifu/PCNextF[49]} {wallypipelinedsoc/hart/ifu/PCNextF[50]} {wallypipelinedsoc/hart/ifu/PCNextF[51]} {wallypipelinedsoc/hart/ifu/PCNextF[52]} {wallypipelinedsoc/hart/ifu/PCNextF[53]} {wallypipelinedsoc/hart/ifu/PCNextF[54]} {wallypipelinedsoc/hart/ifu/PCNextF[55]} {wallypipelinedsoc/hart/ifu/PCNextF[56]} {wallypipelinedsoc/hart/ifu/PCNextF[57]} {wallypipelinedsoc/hart/ifu/PCNextF[58]} {wallypipelinedsoc/hart/ifu/PCNextF[59]} {wallypipelinedsoc/hart/ifu/PCNextF[60]} {wallypipelinedsoc/hart/ifu/PCNextF[61]} {wallypipelinedsoc/hart/ifu/PCNextF[62]} {wallypipelinedsoc/hart/ifu/PCNextF[63]}]]
+
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 6feb8dbd1..3b0643604 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -84,7 +84,7 @@ module ifu (
     output logic                ICacheMiss
 );
 
-  logic [`XLEN-1:0]            PCCorrectE, UnalignedPCNextF, PCNextF;
+(* mark_debug = "true" *)  logic [`XLEN-1:0]            PCCorrectE, UnalignedPCNextF, PCNextF;
   logic                        misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM;
   logic                        PrivilegedChangePCM;
   logic                        IllegalCompInstrD;
@@ -115,7 +115,7 @@ module ifu (
   logic 					   ICacheStallF;
   logic 					   IgnoreRequest;
   logic 					   CPUBusy;
-  logic [31:0] 				   PostSpillInstrRawF;
+(* mark_debug = "true" *)  logic [31:0] 				   PostSpillInstrRawF;
 
   localparam integer   SPILLTHRESHOLD = `MEM_ICACHE ? `ICACHE_LINELENINBITS/32 : 1;