diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index be67c99bd..84d043817 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
+Subproject commit 84d043817f75f752c9873326475e11f16e3a6f7c
diff --git a/addins/riscv-isa-sim b/addins/riscv-isa-sim
index ddcfa6cc3..d22b28019 160000
--- a/addins/riscv-isa-sim
+++ b/addins/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit ddcfa6cc3d80818140a459e590296c3079c5a3ec
+Subproject commit d22b280198e74b871e04fc0ddb622fb825fdae49
diff --git a/wally-pipelined/linux-testgen/linux-testvectors/all.txt b/wally-pipelined/linux-testgen/linux-testvectors/all.txt
new file mode 120000
index 000000000..4275ab31a
--- /dev/null
+++ b/wally-pipelined/linux-testgen/linux-testvectors/all.txt
@@ -0,0 +1 @@
+/courses/e190ax/buildroot_boot/all.txt
\ No newline at end of file
diff --git a/wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt b/wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt
new file mode 120000
index 000000000..33bff4ce4
--- /dev/null
+++ b/wally-pipelined/linux-testgen/linux-testvectors/bootmem.txt
@@ -0,0 +1 @@
+/courses/e190ax/buildroot_boot/bootmem.txt
\ No newline at end of file
diff --git a/wally-pipelined/linux-testgen/linux-testvectors/checkpoint8500000 b/wally-pipelined/linux-testgen/linux-testvectors/checkpoint8500000
new file mode 120000
index 000000000..e48344418
--- /dev/null
+++ b/wally-pipelined/linux-testgen/linux-testvectors/checkpoint8500000
@@ -0,0 +1 @@
+/courses/e190ax/buildroot_boot/checkpoint8500000
\ No newline at end of file
diff --git a/wally-pipelined/linux-testgen/linux-testvectors/ram.txt b/wally-pipelined/linux-testgen/linux-testvectors/ram.txt
new file mode 120000
index 000000000..209d4eed6
--- /dev/null
+++ b/wally-pipelined/linux-testgen/linux-testvectors/ram.txt
@@ -0,0 +1 @@
+/courses/e190ax/buildroot_boot/ram.txt
\ No newline at end of file
diff --git a/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump
new file mode 120000
index 000000000..8f52aac07
--- /dev/null
+++ b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump
@@ -0,0 +1 @@
+/courses/e190ax/buildroot_boot/vmlinux.objdump
\ No newline at end of file
diff --git a/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.addr b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.addr
new file mode 120000
index 000000000..62079f3a2
--- /dev/null
+++ b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.addr
@@ -0,0 +1 @@
+/courses/e190ax/buildroot_boot/vmlinux.objdump.addr
\ No newline at end of file
diff --git a/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.lab b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.lab
new file mode 120000
index 000000000..fe8ecc6e4
--- /dev/null
+++ b/wally-pipelined/linux-testgen/linux-testvectors/vmlinux.objdump.lab
@@ -0,0 +1 @@
+/courses/e190ax/buildroot_boot/vmlinux.objdump.lab
\ No newline at end of file
diff --git a/wally-pipelined/src/ifu/.ifu.sv.swp b/wally-pipelined/src/ifu/.ifu.sv.swp
new file mode 100644
index 000000000..3c7810e18
Binary files /dev/null and b/wally-pipelined/src/ifu/.ifu.sv.swp differ
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index b18d8bc3c..3f9bcf510 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -133,13 +133,21 @@ module ifu (
        .LoadAccessFaultM(),
        .StoreAccessFaultM(),
        .DisableTranslation(1'b0),
-       .Cacheable(),
-       .Idempotent(),
-       .AtomicAllowed(),
-       .*);
+       .Cacheable(), .Idempotent(), .AtomicAllowed(),
+
+       .clk, .reset,
+       .SATP_REGW,
+       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
+       .STATUS_MPP,
+       .PrivilegeModeW,
+       .InstrAccessFaultF,
+       .PMPCFG_ARRAY_REGW, //bitfields?
+       .PMPADDR_ARRAY_REGW      
+       );
 
 
-  // branch predictor signals
+
+  // branch predictor signal
   logic                        SelBPPredF;
   logic [`XLEN-1:0]            BPPredPCF, PCNext0F, PCNext1F, PCNext2F, PCNext3F;
   logic [4:0]                  InstrClassD, InstrClassE;