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Cache code cleanup
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parent
0a25f18a07
commit
057183bcc9
48
pipelined/src/cache/cache.sv
vendored
48
pipelined/src/cache/cache.sv
vendored
@ -145,32 +145,34 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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// Bypass cache array to save a cycle when finishing a load miss
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// Bypass cache array to save a cycle when finishing a load miss
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mux2 #(LINELEN) EarlyReturnMux(ReadDataLineCache, FetchBuffer, SelFetchBuffer, ReadDataLine);
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mux2 #(LINELEN) EarlyReturnMux(ReadDataLineCache, FetchBuffer, SelFetchBuffer, ReadDataLine);
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// Select word from cache line
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subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL) subcachelineread(
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subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL) subcachelineread(
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.PAdr(WordOffsetAddr),
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.PAdr(WordOffsetAddr), .ReadDataLine, .ReadDataWord);
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.ReadDataLine, .ReadDataWord);
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Bus address for fetch, writeback, or flush writeback
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// Write Path: Write data and address. Muxes between writes from bus and writes from CPU.
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/////////////////////////////////////////////////////////////////////////////////////////////
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onehotdecoder #(LOGCWPL) adrdec(
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.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded));
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for(index = 0; index < 2**LOGCWPL; index++) begin
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assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
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end
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assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1.
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assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
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for(index = 0; index < LINELEN/8; index++) begin
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mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
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.d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index]));
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end
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mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
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mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
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.d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
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.d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
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.d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}),
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.d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}),
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.s({SelFlush, SelWriteback}), .y(CacheBusAdr));
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.s({SelFlush, SelWriteback}), .y(CacheBusAdr));
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Write Path
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Adjust byte mask from word to cache line
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onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded));
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for(index = 0; index < 2**LOGCWPL; index++) begin
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assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
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end
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assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1.
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assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
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// Merge write data into fetched cache line for store miss
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for(index = 0; index < LINELEN/8; index++) begin
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mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
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.d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index]));
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end
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Flush address and way generation during flush
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// Flush address and way generation during flush
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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@ -189,15 +191,13 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Cache FSM
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// Cache FSM
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
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cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
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.FlushStage, .CacheRW, .CacheAtomic, .Stall,
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.FlushStage, .CacheRW, .CacheAtomic, .Stall,
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.CacheHit, .LineDirty, .CacheStall, .CacheCommitted,
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.CacheHit, .LineDirty, .CacheStall, .CacheCommitted,
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.CacheMiss, .CacheAccess, .SelAdr,
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.CacheMiss, .CacheAccess, .SelAdr,
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.ClearValid, .ClearDirty, .SetDirty,
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.ClearValid, .ClearDirty, .SetDirty, .SetValid, .SelWriteback, .SelFlush,
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.SetValid, .SelWriteback, .SelFlush,
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.FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
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.FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
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.FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
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.FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
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.InvalidateCache,
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.InvalidateCache, .CacheEn, .LRUWriteEn);
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.CacheEn,
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.LRUWriteEn);
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endmodule
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endmodule
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