From 468fa7528f5742e5a21566ea031fc57df6761f9c Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Jan 2021 10:19:09 -0500 Subject: [PATCH 1/3] Initial checkin of UART --- wally-pipelined/src/dmem.sv | 15 +- wally-pipelined/src/gpio.sv | 7 +- wally-pipelined/src/testbench.sv | 3 +- wally-pipelined/src/uart.sv | 84 +++++ wally-pipelined/src/uartPC16550D.sv | 476 ++++++++++++++++++++++++++ wally-pipelined/src/wally-macros.sv | 9 + wally-pipelined/src/wallypipelined.sv | 4 +- 7 files changed, 591 insertions(+), 7 deletions(-) create mode 100644 wally-pipelined/src/uart.sv create mode 100644 wally-pipelined/src/uartPC16550D.sv diff --git a/wally-pipelined/src/dmem.sv b/wally-pipelined/src/dmem.sv index 1cab372be..c6f02c9a9 100644 --- a/wally-pipelined/src/dmem.sv +++ b/wally-pipelined/src/dmem.sv @@ -36,12 +36,15 @@ module dmem #(parameter XLEN=32) ( output logic DataAccessFaultM, output logic TimerIntM, SwIntM, input logic [31:0] GPIOPinsIn, - output logic [31:0] GPIOPinsOut, GPIOPinsEn); + output logic [31:0] GPIOPinsOut, GPIOPinsEn, + input logic UARTSin, + output logic UARTSout); logic [XLEN-1:0] MaskedWriteDataM; - logic [XLEN-1:0] RdTimM, RdCLINTM, RdGPIOM; - logic TimEnM, CLINTEnM, GPIOEnM; + logic [XLEN-1:0] RdTimM, RdCLINTM, RdGPIOM, RdUARTM; + logic TimEnM, CLINTEnM, GPIOEnM, UARTEnM; logic [1:0] MemRWdtimM, MemRWclintM, MemRWgpioM; + logic UARTIntr;// *** will need to tie INTR to an interrupt handler // Address decoding generate @@ -52,6 +55,7 @@ module dmem #(parameter XLEN=32) ( endgenerate assign CLINTEnM = ~(|AdrM[XLEN-1:26]) & AdrM[25] & ~(|AdrM[24:16]); // 0x02000000-0x0200FFFF assign GPIOEnM = (AdrM[31:8] == 24'h10012); // 0x10012000-0x100120FF + assign UARTEnM = ~(|AdrM[XLEN-1:29]) & AdrM[28] & ~(|AdrM[27:3]); // 0x10000000-0x10000007 assign MemRWdtimM = MemRWM & {2{TimEnM}}; assign MemRWclintM = MemRWM & {2{CLINTEnM}}; @@ -62,7 +66,10 @@ module dmem #(parameter XLEN=32) ( // memory-mapped I/O peripherals clint #(XLEN) clint(.AdrM(AdrM[15:0]), .*); - gpio #(XLEN) gpio(.AdrM(AdrM[7:0]), .*); + gpio #(XLEN) gpio(.AdrM(AdrM[7:0]), .*); // *** may want to add GPIO interrupts + uart #(XLEN) uart(.TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout), + .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), + .RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*); // *** add cache and interface to external memory & other peripherals diff --git a/wally-pipelined/src/gpio.sv b/wally-pipelined/src/gpio.sv index 0952fe210..8723cb98a 100644 --- a/wally-pipelined/src/gpio.sv +++ b/wally-pipelined/src/gpio.sv @@ -53,7 +53,12 @@ module gpio #(parameter XLEN=32) ( assign #2 entry = {AdrM[7:2], 2'b00}; endgenerate - assign INPUT_VAL = GPIOPinsIn & INPUT_EN; + generate + if (`GPIO_LOOPBACK_TEST) // connect OUT to IN for loopback testing + assign INPUT_VAL = GPIOPinsOut & INPUT_EN & OUTPUT_EN; + else + assign INPUT_VAL = GPIOPinsIn & INPUT_EN; + endgenerate assign GPIOPinsOut = OUTPUT_VAL; assign GPIOPinsEn = OUTPUT_EN; diff --git a/wally-pipelined/src/testbench.sv b/wally-pipelined/src/testbench.sv index 190a631eb..2fbc678aa 100644 --- a/wally-pipelined/src/testbench.sv +++ b/wally-pipelined/src/testbench.sv @@ -236,12 +236,13 @@ string tests32i[] = { string signame, memfilename; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; + logic UARTSin, UARTSout; // instantiate device to be tested assign GPIOPinsIn = 0; wallypipelined #(XLEN, MISA, ZCSR, ZCOUNTERS) dut( clk, reset, WriteData, DataAdr, MemRW, - GPIOPinsIn, GPIOPinsOut, GPIOPinsEn + GPIOPinsIn, GPIOPinsOut, GPIOPinsEn, UARTSin, UARTSout ); // Track names of instructions diff --git a/wally-pipelined/src/uart.sv b/wally-pipelined/src/uart.sv new file mode 100644 index 000000000..31e001dbb --- /dev/null +++ b/wally-pipelined/src/uart.sv @@ -0,0 +1,84 @@ +/////////////////////////////////////////// +// uart.sv +// +// Written: David_Harris@hmc.edu 21 January 2021 +// Modified: +// +// Purpose: Interface to Universial Asynchronous Receiver/ Transmitter with FIFOs +// Emulates interface of Texas Instruments PC165550D +// Compatible with UART in Imperas Virtio model *** +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-macros.sv" + +module uart #(parameter XLEN=32) ( + input logic clk, reset, + input logic [1:0] MemRWgpioM, + input logic [7:0] ByteMaskM, + input logic [XLEN-1:0] AdrM, + input logic [XLEN-1:0] MaskedWriteDataM, + output logic [XLEN-1:0] RdUARTM, + input logic SIN, DSRb, DCDb, CTSb, RIb, // from E1A driver from RS232 interface + output logic SOUT, RTSb, DTRb, // to E1A driver to RS232 interface + output logic OUT1b, OUT2b, INTR, TXRDYb, RXRDYb); // to CPU + + // UART interface signals + logic [2:0] A; + logic MEMRb, MEMWb; + logic [7:0] Din, Dout; + logic SINint; // for loopback testing + + // rename processor interface signals to match PC16550D and provide one-byte interface + assign MEMRb = ~MemRWgpioM[1]; + assign MEMWb = ~MemRWgpioM[0]; + assign A = AdrM[2:0]; + + generate + if (XLEN == 64) begin + always_comb begin +/* RdUARTM = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout}; + case (AdrM[2:0]) + 3'b000: Din = MaskedWriteDataM[7:0]; + 3'b001: Din = MaskedWriteDataM[15:8]; + 3'b010: Din = MaskedWriteDataM[23:16]; + 3'b011: Din = MaskedWriteDataM[31:24]; + 3'b100: Din = MaskedWriteDataM[39:32]; + 3'b101: Din = MaskedWriteDataM[47:40]; + 3'b110: Din = MaskedWriteDataM[55:48]; + 3'b111: Din = MaskedWriteDataM[63:56]; + endcase */ + end + end else begin // 32-bit + always_comb begin + RdUARTM = {Dout, Dout, Dout, Dout}; + case (AdrM[1:0]) + 2'b00: Din = MaskedWriteDataM[7:0]; + 2'b01: Din = MaskedWriteDataM[15:8]; + 2'b10: Din = MaskedWriteDataM[23:16]; + 2'b11: Din = MaskedWriteDataM[31:24]; + endcase + end + end + endgenerate + + logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK + uartPC16550D u(.RCLK(BAUDOUTb), .*); + +endmodule + diff --git a/wally-pipelined/src/uartPC16550D.sv b/wally-pipelined/src/uartPC16550D.sv new file mode 100644 index 000000000..62037cc62 --- /dev/null +++ b/wally-pipelined/src/uartPC16550D.sv @@ -0,0 +1,476 @@ +/////////////////////////////////////////// +// uart.sv +// +// Written: David_Harris@hmc.edu 21 January 2021 +// Modified: +// +// Purpose: Universial Asynchronous Receiver/ Transmitter with FIFOs +// Emulates interface of Texas Instruments PC16550D +// Compatible with UART in Imperas Virtio model *** +// +// Compatible with most of PC16550D with the following known exceptions: +// Generates 2 rather than 1.5 stop bits when 5-bit word length is slected and LCR[2] = 1 +// Timeout not ye implemented*** +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-macros.sv" + +module uartPC16550D( + // Processor Interface + input logic clk, reset, + input logic [2:0] A, + input logic [7:0] Din, + output logic [7:0] Dout, + input logic MEMRb, MEMWb, + output logic INTR, TXRDYb, RXRDYb, + // Clocks + output logic BAUDOUTb, + input logic RCLK, + // E1A Driver + input logic SIN, DSRb, DCDb, CTSb, RIb, + output logic SOUT, RTSb, DTRb, OUT1b, OUT2b +); + + // transmit and receive states + typedef enum {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype; + + // Registers + logic [10:0] RBR; + logic [7:0] IIR, FCR, LCR, LSR, SCR, DLL, DLM; + logic [3:0] IER, MSR; + logic [4:0] MCR; + + // Syncrhonized and delayed UART signals + logic SINd, DSRbd, DCDbd, CTSbd, RIbd; + logic SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync; + logic DSRb2, DCDb2, CTSb2, RIb2; + logic SOUTbit; + + // Control signals + logic loop; // loopback mode + logic DLAB; // Divisor Latch Access Bit (LCR bit 7) + + // Baud and rx/tx timing + logic baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period + logic [23:0] baudcount; + logic [3:0] rxoversampledcnt, txoversampledcnt; // count oversampled-by-16 + logic [3:0] rxbitsreceived, txbitssent; + statetype rxstate, txstate; + + // shift registrs and FIFOs + logic [9:0] rxshiftreg; + logic [11:0] txshiftreg; + logic [10:0] rxfifo[15:0]; + logic [7:0] txfifo[15:0]; + logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel; + logic [3:0] rxfifoentries, txfifoentries; + logic [3:0] rxbitsexpected, txbitsexpected; + + // receive data + logic [10:0] RXBR; + logic [6:0] rxtimeoutcnt; + logic rxcentered; + logic rxparity, rxparitybit, rxstopbit; + logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr; + logic rxdataready; + logic rxfifoempty, rxfifotriggered, rxfifotimeout; + logic rxfifodmaready; + logic [8:0] rxdata9; + logic [7:0] rxdata; + logic [15:0] rxerrbit, rxfullbit; + + // transmit data + logic [11:0] TXHR, txdata, nexttxdata, txsr; + logic txnextbit, txhrfull, txsrfull; + logic txparity; + logic txfifoempty, txfifofull, txfifodmaready; + + // control signals + logic fifoenabled, fifodmamodesel, evenparitysel; + + // interrupts + logic rxlinestatusintr, rxdataavailintr, txhremptyintr, modemstatusintr, intrpending; + logic [2:0] intrid; + + /////////////////////////////////////////// + // Input synchronization: 2-stage synchronizer + /////////////////////////////////////////// + always_ff @(posedge clk) begin + {SINd, DSRbd, DCDbd, CTSbd, RIbd} <= {SIN, DSRb, DCDb, CTSb, RIb}; + {SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} : + {SINd, DSRbd, DCDbd, CTSbd, RIbd}; // syncrhonized signals, handle loopback testing + {DSRb2, DCDb2, CTSb2, RIb2} <= {DSRbsync, DCDbsync, CTSbsync, RIbsync}; // for detecting state changes + end + + /////////////////////////////////////////// + // Register interface (Table 1, note some are read only and some write only) + /////////////////////////////////////////// + always_ff @(posedge clk, posedge reset) + if (reset) begin // Table 3 Reset Configuration + IER <= 4'b0; + IIR <= 8'b1; + FCR <= 8'b0; + LCR <= 8'b0; + MCR <= 5'b0; + LSR <= 8'b01100000; + MSR <= 4'b0; + DLL <= 8'b0; + DLM <= 8'b0; + SCR <= 8'b0; // not strictly necessary to reset + end else begin + if (~MEMWb) begin + case (A) + 3'b000: if (DLAB) DLL <= Din; // else TXHR <= Din; // TX handled in TX register/FIFO section + 3'b001: if (DLAB) DLM <= Din; else IER <= Din[3:0]; + 3'b010: FCR <= {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing + 3'b011: LCR <= Din; + 3'b100: MCR <= Din[4:0]; + 3'b101: LSR[6:1] <= Din[6:1]; // recommended only for test, see 8.6.3 + 3'b110: MSR <= Din[3:0]; + 3'b111: SCR <= Din; + endcase + end else if (~MEMRb) begin + /* verilator lint_off CASEINCOMPLETE */ + case (A) + 3'b101: begin // clear some LSR bits on read + LSR[4:1] <= 0; + LSR[7] <= 0; + end + 3'b110: MSR[1:0] <= 4'b0; // clear status bits on read + endcase + /* verilator lint_on CASEINCOMPLETE */ + end + // Line Status Register (8.6.3) + LSR[0] = rxdataready; // Data ready + if (RXBR[10]) LSR[1] = 1; // overrun error + if (RXBR[9]) LSR[2] = 1; // parity error + if (RXBR[8]) LSR[3] = 1; // framing error + if (rxbreak) LSR[4] = 1; // break indicator + LSR[5] = txhremptyintr ; // THRE + LSR[6] = ~txsrfull & txhremptyintr; // TEMT + if (rxfifohaserr) LSR[7] = 1; // any bits in FIFO have error + + // Modem Status Register (8.6.8) + MSR[0] |= CTSb2 ^ CTSbsync; // Delta Clear to Send + MSR[1] |= DSRb2 ^ DSRbsync; // Delta Data Set Ready + MSR[2] |= (~RIb2 & RIbsync); // Trailing Edge of Ring Indicator + MSR[3] |= DCDb2 ^ DCDbsync; // Delta Data Carrier Detect + end + + always_comb + if (~MEMRb) + case (A) + 3'b000: if (DLAB) Dout = DLL; else Dout = RBR; + 3'b001: if (DLAB) Dout = DLM; else Dout = {4'b0, IER[3:0]}; + 3'b010: Dout = {{2{fifoenabled}}, 2'b00, intrid[2:0], ~intrpending}; // Read only Interupt Ident Register + 3'b011: Dout = LCR; + 3'b100: Dout = {3'b000, MCR}; + 3'b101: Dout = LSR; + 3'b110: Dout = {~CTSbsync, ~DSRbsync, ~RIbsync, ~DCDbsync, MSR[3:0]}; + 3'b111: Dout = SCR; + endcase + else Dout = 8'b0; + + /////////////////////////////////////////// + // Baud rate generator + // consider switching to same fixed-frequency reference clock used for TIME register + // prescale by factor of 2^UART_PRESCALE to allow for high-frequency reference clock + // Unlike PC16550D, this unit is hardwired with same rx and tx baud clock + // *** add table of scale factors to get 16x uart clk + /////////////////////////////////////////// + always_ff @(posedge clk, posedge reset) + if (reset) begin + baudcount <= 0; + baudpulse <= 0; + end else begin + baudpulse <= (baudcount == {DLM, DLL, {(`UART_PRESCALE){1'b0}}}); + baudcount <= baudpulse ? 0 : baudcount +1; + end + assign txbaudpulse = baudpulse; + assign BAUDOUTb = ~baudpulse; + assign rxbaudpulse = ~RCLK; // usually BAUDOUTb tied to RCLK externally + + /////////////////////////////////////////// + // receive timing and control + /////////////////////////////////////////// + + always_ff @(posedge clk, posedge reset) + if (reset) begin + rxoversampledcnt <= 0; + rxstate = UART_IDLE; + rxbitsreceived <= 0; + rxtimeoutcnt <= 0; + end else begin + if (rxstate == UART_IDLE & ~SINsync) begin // got start bit + rxstate = UART_ACTIVE; + rxoversampledcnt <= 0; + rxbitsreceived <= 0; + rxtimeoutcnt <= 0; // reset timeout when new character is arriving + end else if (rxbaudpulse & (rxstate == UART_ACTIVE)) begin + rxoversampledcnt <= rxoversampledcnt + 1; // 16x oversampled counter + if (rxcentered) rxbitsreceived <= rxbitsreceived + 1; + if (rxbitsreceived == rxbitsexpected) rxstate <= UART_DONE; // pulse rxdone for a cycle + end else if (rxstate == UART_DONE || rxstate == UART_BREAK) begin + if (rxbreak & ~SINsync) rxstate <= UART_BREAK; + else rxstate <= UART_IDLE; + end + // timeout counting + if (~MEMRb && A == 3'b000 && ~DLAB) rxtimeoutcnt <= 0; // reset timeout on read + else if (fifoenabled & ~rxfifoempty & rxbaudpulse & ~rxfifotimeout) rxtimeoutcnt <= rxtimeoutcnt+1; // *** not right + end + + assign rxcentered = rxbaudpulse && (rxoversampledcnt == 4'b1000); // implies rxstate = UART_ACTIVE + assign rxbitsexpected = 1 + (5 + LCR[1:0]) + LCR[3] + 1; // start bit + data bits + (parity bit) + stop bit + + /////////////////////////////////////////// + // receive shift register, buffer register, FIFO + /////////////////////////////////////////// + always_ff @(posedge clk, posedge reset) + if (reset) rxshiftreg <= 0; + else if (rxcentered) rxshiftreg <= {rxshiftreg[8:0], SINsync}; // capture bit + assign rxparitybit = rxshiftreg[1]; // parity, if it exists, in bit 1 when all done + assign rxstopbit = rxshiftreg[0]; + always_comb + case(LCR[1:0]) // check how many bits used. Grab all bits including possible parity + 2'b00: rxdata9 = {3'b0, rxshiftreg[6:1]}; // 5-bit character + 2'b01: rxdata9 = {2'b0, rxshiftreg[7:1]}; // 6-bit + 2'b10: rxdata9 = {1'b0, rxshiftreg[8:1]}; // 7-bit + 2'b11: rxdata9 = rxshiftreg[9:1]; + endcase + assign rxdata = LCR[3] ? rxdata9[8:1] : rxdata9[7:0]; // discard parity bit + + // ERROR CONDITIONS + assign rxparity = ^rxdata; + assign rxparityerr = rxparity ^ rxparitybit ^ ~evenparitysel; // Check even/odd parity (*** check if LCR needs to be inverted) + assign rxoverrunerr = fifoenabled ? (rxfifoentries == 15) : rxdataready; // overrun if FIFO or receive buffer register full + assign rxframingerr = ~rxstopbit; // framing error if no stop bit + assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time + + // receive FIFO and register + always_ff @(posedge clk, posedge reset) + if (reset) begin + rxfifohead <= 0; rxfifotail <= 0; rxdataready <= 0; RXBR <= 0; + end else begin + if (rxstate == UART_DONE) begin + RXBR = {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register + if (fifoenabled) begin + rxfifo[rxfifohead] <= RXBR; + rxfifohead <= rxfifohead + 1; + end + rxdataready <= 1; + end else if (~MEMRb && A == 3'b000 && ~DLAB) begin // reading RBR updates ready / pops fifo + if (fifoenabled) begin + rxfifotail = rxfifotail + 1; + if (rxfifohead == rxfifotail) rxdataready <= 0; + end else rxdataready <= 0; + end else if (~MEMWb && A == 3'b010) // writes to FIFO Control Register + if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents + rxfifohead <= 0; rxfifotail <= 0; + end + end + + assign rxfifoempty = (rxfifohead == rxfifotail); + assign rxfifoentries = (rxfifohead >= rxfifotail) ? (rxfifohead-rxfifotail) : + (rxfifohead + 16 - rxfifotail); + assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel; + //assign rxfifotimeout = rxtimeoutcnt[6]; // time out after 4 character periods; *** probably not right yet + assign rxfifotimeout = 0; // disabled pending fix + + // detect any errors in rx fifo + generate + genvar i; + for (i=0; i<16; i++) begin + assign rxerrbit[i] = |rxfifo[i][10:8]; // are any of the error conditions set? + if (i > 0) + assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i); + else + assign rxfullbit[0] = ((rxfifohead==i) | rxfullbit[15]) & (rxfifotail != i); + end + endgenerate + assign rxfifohaserr = |(rxerrbit & rxfullbit); + + // receive buffer register and ready bit + always_ff @(posedge clk, posedge reset) // track rxrdy for DMA mode (FCR3 = FCR0 = 1) + if (reset) rxfifodmaready <= 0; + else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= 1; + else if (rxfifoempty) rxfifodmaready <= 0; + + always_comb + if (fifoenabled) begin + if (rxfifoempty) RBR = 11'b0; + else RBR = rxfifo[rxfifotail]; + if (fifodmamodesel) RXRDYb = ~rxfifodmaready; + else RXRDYb = rxfifoempty; + end else begin + RBR = RXBR; + RXRDYb = ~rxdataready; + end + + /////////////////////////////////////////// + // transmit timing and control + /////////////////////////////////////////// + always_ff @(posedge clk, posedge reset) + if (reset) begin + txoversampledcnt <= 0; + txstate <= UART_IDLE; + txbitssent <= 0; + end else if ((txstate == UART_IDLE) && txsrfull) begin // start transmitting + txstate <= UART_ACTIVE; + txoversampledcnt <= 0; + txbitssent <= 0; + end else if (txbaudpulse & (txstate == UART_ACTIVE)) begin + txoversampledcnt <= txoversampledcnt + 1; + if (txnextbit) begin // transmit at end of phase + txbitssent <= txbitssent+1; + if (txbitssent == txbitsexpected) txstate <= UART_DONE; + end + end else if (txstate == UART_DONE) begin + txstate <= UART_IDLE; + end + + assign txbitsexpected = 1 + (5 + LCR[1:0]) + LCR[3] + 1 + LCR[2] - 1; // start bit + data bits + (parity bit) + stop bit(s) + assign txnextbit = txbaudpulse && (txoversampledcnt == 4'b0000); // implies txstate = UART_ACTIVE + + /////////////////////////////////////////// + // transmit holding register, shift register, FIFO + /////////////////////////////////////////// + + always_comb begin // compute value for parity and tx holding register + nexttxdata = fifoenabled ? txfifo[txfifotail] : TXHR; // pick from FIFO or holding register + case (LCR[1:0]) // compute parity from appropriate number of bits + 2'b00: txparity = ^nexttxdata[4:0] ^ ~evenparitysel; // *** check polarity + 2'b01: txparity = ^nexttxdata[5:0] ^ ~evenparitysel; + 2'b10: txparity = ^nexttxdata[6:0] ^ ~evenparitysel; + 2'b11: txparity = ^nexttxdata[7:0] ^ ~evenparitysel; + endcase + case({LCR[3], LCR[1:0]}) // parity, data bits + // load up start bit (0), 5-8 data bits, 0-1 parity bits, 2 stop bits (only one sometimes used), padding + 3'b000: txdata = {1'b0, nexttxdata[4:0], 6'b111111}; // 5 data, no parity + 3'b001: txdata = {1'b0, nexttxdata[5:0], 5'b11111}; // 6 data, no parity + 3'b010: txdata = {1'b0, nexttxdata[6:0], 4'b1111}; // 7 data, no parity + 3'b011: txdata = {1'b0, nexttxdata[7:0], 3'b111}; // 8 data, no parity + 3'b100: txdata = {1'b0, nexttxdata[4:0], txparity, 5'b11111}; // 5 data, parity + 3'b101: txdata = {1'b0, nexttxdata[5:0], txparity, 4'b1111}; // 6 data, parity + 3'b110: txdata = {1'b0, nexttxdata[6:0], txparity, 3'b111}; // 7 data, parity + 3'b111: txdata = {1'b0, nexttxdata[7:0], txparity, 2'b11}; // 8 data, parity + endcase + end + + // registers & FIFO + always_ff @(posedge clk, posedge reset) + if (reset) begin + txfifohead <= 0; txfifotail <= 0; txhrfull <= 0; txsrfull <= 0; TXHR <= 0; txsr <= 0; + end else begin + if (~MEMWb && A == 3'b000 && ~DLAB) begin // writing transmit holding register or fifo + if (fifoenabled) begin + txfifo[txfifohead] <= Din; + txfifohead <= txfifohead + 1; + end else begin + TXHR <= Din; + txhrfull <= 1; + end + $display("UART transmits: %c",Din); // for testbench + end + if (txstate == UART_IDLE) // move data into tx shift register if available + if (fifoenabled) + if (~txfifoempty) begin + txsr <= txdata; + txfifotail <= txfifotail+1; + txsrfull <= 1; + end + else if (txhrfull) begin + txsr <= txdata; + txhrfull <= 0; + txsrfull <= 1; + end + else if (txstate == UART_DONE) txsrfull <= 0; // done transmitting shift register + else if (txstate == UART_ACTIVE && txnextbit) TXHR <= {TXHR[10:0], 1'b1}; // shift txhr + if (!MEMWb && A == 3'b010) // writes to FIFO control register + if (Din[2] | ~Din[0]) begin // tx FIFO reste or FIFO disable clears FIFO contents + txfifohead <= 0; txfifotail <= 0; + end + end + + assign txfifoempty = (txfifohead == txfifotail); + assign txfifoentries = (txfifohead >= txfifotail) ? (txfifohead-txfifotail) : + (txfifohead + 16 - txfifotail); + assign txfifofull = (txfifoentries == 4'b1111); + + // transmit buffer ready bit + always_ff @(posedge clk, posedge reset) // track txrdy for DMA mode (FCR3 = FCR0 = 1) + if (reset) txfifodmaready <= 0; + else if (txfifoempty) txfifodmaready <= 1; + else if (txfifofull) txfifodmaready <= 0; + + always_comb + if (fifoenabled & fifodmamodesel) TXRDYb = ~txfifodmaready; + else TXRDYb = ~txhremptyintr; + + // Transmitter pin + assign SOUTbit = TXHR[11]; // transmit most significant bit + assign SOUT = loop ? 1 : (LCR[6] ? 0 : SOUTbit); // tied to 1 during loopback or 0 during break + + /////////////////////////////////////////// + // interrupts + /////////////////////////////////////////// + + assign rxlinestatusintr = |LSR[4:1]; // LS interrupt if any of the flags are true + assign rxdataavailintr = fifoenabled ? rxfifotriggered : rxdataready; + assign txhremptyintr = fifoenabled ? txfifoempty : ~txhrfull; + assign modemstatusintr = |MSR[3:0]; // set interrupt when modem pins change + + // interrupt priority (Table 5) + // set intrid based on highest priority pending interrupt source; otherwise, no interrupt is pending + always_comb begin + intrpending = 1; + if (rxlinestatusintr & IER[2]) intrid = 3'b011; + else if (rxdataavailintr & IER[0]) intrid = 3'b010; + else if (rxfifotimeout & fifoenabled & IER[0]) intrid = 3'b110; + else if (txhremptyintr & IER[1]) intrid = 3'b001; + else if (modemstatusintr & IER[3]) intrid = 3'b000; + else begin + intrid = 3'b000; + intrpending = 0; + end + end + always @(posedge clk) INTR <= intrpending; // prevent glitches on interrupt pin + + /////////////////////////////////////////// + // modem control logic + /////////////////////////////////////////// + + assign loop = MCR[4]; + assign DTRb = ~MCR[0] | loop; // disable modem signals in loopback mode + assign RTSb = ~MCR[1] | loop; + assign OUT1b = ~MCR[2] | loop; + assign OUT2b = ~MCR[3] | loop; + + assign DLAB = LCR[7]; + assign evenparitysel = LCR[4]; + assign fifoenabled = FCR[0]; + assign fifodmamodesel = FCR[3]; + always_comb + case (FCR[7:6]) + 2'b00: rxfifotriggerlevel = 1; + 2'b01: rxfifotriggerlevel = 4; + 2'b10: rxfifotriggerlevel = 8; + 2'b11: rxfifotriggerlevel = 14; + endcase + +endmodule diff --git a/wally-pipelined/src/wally-macros.sv b/wally-pipelined/src/wally-macros.sv index 9ff616176..c52e206d9 100644 --- a/wally-pipelined/src/wally-macros.sv +++ b/wally-pipelined/src/wally-macros.sv @@ -20,5 +20,14 @@ `define S_MODE (2'b01) `define U_MODE (2'b00) +// Test modes + +// Tie GPIO outputs back to inputs +`define GPIO_LOOPBACK_TEST 0 + + +// Hardware configuration +`define UART_PRESCALE 1 + /* verilator lint_off STMTDLY */ /* verilator lint_off WIDTH */ diff --git a/wally-pipelined/src/wallypipelined.sv b/wally-pipelined/src/wallypipelined.sv index 762e260af..bec09fd6b 100644 --- a/wally-pipelined/src/wallypipelined.sv +++ b/wally-pipelined/src/wallypipelined.sv @@ -57,7 +57,9 @@ module wallypipelined #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) ( output logic [XLEN-1:0] WriteDataM, DataAdrM, output logic [1:0] MemRWM, input logic [31:0] GPIOPinsIn, - output logic [31:0] GPIOPinsOut, GPIOPinsEn + output logic [31:0] GPIOPinsOut, GPIOPinsEn, + input logic UARTSin, + output logic UARTSout ); logic [XLEN-1:0] PCF, ReadDataM; From ff4da36e3d92a65dd94221da811bd4ccbd9b4fda Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Jan 2021 10:22:20 -0500 Subject: [PATCH 2/3] Cleaned up regfile x0 tied to gnd --- wally-pipelined/src/regfile.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/src/regfile.sv b/wally-pipelined/src/regfile.sv index 78238a823..738683efd 100644 --- a/wally-pipelined/src/regfile.sv +++ b/wally-pipelined/src/regfile.sv @@ -44,8 +44,8 @@ module regfile #(parameter XLEN=32) ( // reset is intended for simulation only, not synthesis always_ff @(negedge clk or posedge reset) - if (reset) for(i=0; i<32; i++) rf[i] <= 0; - else if (we3 & (a3 != 0)) rf[a3] <= wd3; + if (reset) for(i=1; i<32; i++) rf[i] <= 0; + else if (we3) rf[a3] <= wd3; assign #2 rd1 = (a1 != 0) ? rf[a1] : 0; assign #2 rd2 = (a2 != 0) ? rf[a2] : 0; From 2046b810fc01493db4dd1b445b149e05291250c5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Jan 2021 10:48:12 -0500 Subject: [PATCH 3/3] Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh --- wally-pipelined/src/alu.sv | 2 +- wally-pipelined/src/clint.sv | 12 +-- wally-pipelined/src/controller.sv | 2 +- wally-pipelined/src/csr.sv | 99 +++++--------------- wally-pipelined/src/csrc.sv | 32 +++---- wally-pipelined/src/csri.sv | 10 +- wally-pipelined/src/csrm.sv | 53 +++++------ wally-pipelined/src/csrn.sv | 36 ++++---- wally-pipelined/src/csrs.sv | 44 ++++----- wally-pipelined/src/csrsr.sv | 10 +- wally-pipelined/src/csru.sv | 14 +-- wally-pipelined/src/datapath.sv | 108 +++++++++++----------- wally-pipelined/src/dmem.sv | 36 ++++---- wally-pipelined/src/dtim.sv | 16 ++-- wally-pipelined/src/extend.sv | 16 ++-- wally-pipelined/src/flop.sv | 2 +- wally-pipelined/src/gpio.sv | 12 +-- wally-pipelined/src/hazard.sv | 2 +- wally-pipelined/src/imem.sv | 16 ++-- wally-pipelined/src/instrDecompress.sv | 16 ++-- wally-pipelined/src/memdp.sv | 16 ++-- wally-pipelined/src/mux.sv | 2 +- wally-pipelined/src/pclogic.sv | 34 +++---- wally-pipelined/src/privilegeDecoder.sv | 4 +- wally-pipelined/src/privilegeModeReg.sv | 10 +- wally-pipelined/src/privileged.sv | 28 +++--- wally-pipelined/src/regfile.sv | 10 +- wally-pipelined/src/shifter.sv | 4 +- wally-pipelined/src/testbench.sv | 28 +++--- wally-pipelined/src/trap.sv | 26 +++--- wally-pipelined/src/uart.sv | 12 +-- wally-pipelined/src/uartPC16550D.sv | 2 +- wally-pipelined/src/wally-config.vh | 67 ++++++++++++++ wally-pipelined/src/wallypipelined.sv | 14 +-- wally-pipelined/src/wallypipelinedhart.sv | 14 +-- 35 files changed, 411 insertions(+), 398 deletions(-) create mode 100644 wally-pipelined/src/wally-config.vh diff --git a/wally-pipelined/src/alu.sv b/wally-pipelined/src/alu.sv index 3abf601fb..48d5f3add 100644 --- a/wally-pipelined/src/alu.sv +++ b/wally-pipelined/src/alu.sv @@ -23,7 +23,7 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] a, b, diff --git a/wally-pipelined/src/clint.sv b/wally-pipelined/src/clint.sv index 77c0f76db..dbdd1787d 100644 --- a/wally-pipelined/src/clint.sv +++ b/wally-pipelined/src/clint.sv @@ -24,14 +24,14 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module clint #(parameter XLEN=32) ( +module clint ( input logic clk, reset, input logic [1:0] MemRWclintM, input logic [15:0] AdrM, - input logic [XLEN-1:0] MaskedWriteDataM, - output logic [XLEN-1:0] RdCLINTM, + input logic [`XLEN-1:0] MaskedWriteDataM, + output logic [`XLEN-1:0] RdCLINTM, output logic TimerIntM, SwIntM); logic [63:0] MTIMECMP, MTIME; @@ -45,7 +45,7 @@ module clint #(parameter XLEN=32) ( // word aligned reads generate - if (XLEN==64) + if (`XLEN==64) assign #2 entry = {AdrM[15:3], 3'b000}; else assign #2 entry = {AdrM[15:2], 2'b00}; @@ -54,7 +54,7 @@ module clint #(parameter XLEN=32) ( // register access generate - if (XLEN==64) begin + if (`XLEN==64) begin always_comb begin case(entry) 16'h0000: RdCLINTM = {63'b0, MSIP}; diff --git a/wally-pipelined/src/controller.sv b/wally-pipelined/src/controller.sv index fd562f9b7..3adf9ad45 100644 --- a/wally-pipelined/src/controller.sv +++ b/wally-pipelined/src/controller.sv @@ -23,7 +23,7 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" module controller( diff --git a/wally-pipelined/src/csr.sv b/wally-pipelined/src/csr.sv index 5af0cc0e1..37c82450a 100644 --- a/wally-pipelined/src/csr.sv +++ b/wally-pipelined/src/csr.sv @@ -24,43 +24,43 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module csr #(parameter XLEN = 64, MISA = 0, ZCSR = 1, ZCOUNTERS = 1) ( +module csr ( input logic clk, reset, input logic [31:0] InstrM, - input logic [XLEN-1:0] PCM, SrcAM, + input logic [`XLEN-1:0] PCM, SrcAM, input logic CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, input logic TimerIntM, ExtIntM, SwIntM, input logic InstrValidW, FloatRegWriteW, LoadStallD, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, - input logic [XLEN-1:0] CauseM, NextFaultMtvalM, + input logic [`XLEN-1:0] CauseM, NextFaultMtvalM, output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, - output logic [XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, - output logic [XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, + output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, + output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, output logic [11:0] MIP_REGW, MIE_REGW, output logic STATUS_MIE, STATUS_SIE, input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, - output logic [XLEN-1:0] CSRReadValM, + output logic [`XLEN-1:0] CSRReadValM, output logic IllegalCSRAccessM ); - logic [XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRNReadValM, CSRCReadValM; - logic [XLEN-1:0] CSRSrcM, CSRRWM, CSRRSM, CSRRCM, CSRWriteValM; + logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRNReadValM, CSRCReadValM; + logic [`XLEN-1:0] CSRSrcM, CSRRWM, CSRRSM, CSRRCM, CSRWriteValM; - logic [XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW; + logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW; logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW; logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM; logic CSRMWriteM, CSRSWriteM, CSRUWriteM; logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM; - logic [XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM; + logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM; - logic [XLEN-1:0] zero = 0; - logic [XLEN-1:0] resetExceptionVector = {{(XLEN-32){1'b0}}, 32'h80000000}; // initial exception vector at reset + logic [`XLEN-1:0] zero = 0; + logic [`XLEN-1:0] resetExceptionVector = {{(`XLEN-32){1'b0}}, 32'h80000000}; // initial exception vector at reset logic [11:0] CSRAdrM; logic [11:0] SIP_REGW, SIE_REGW; @@ -72,7 +72,7 @@ module csr #(parameter XLEN = 64, MISA = 0, ZCSR = 1, ZCOUNTERS = 1) ( // modify CSRs always_comb begin // Choose either rs1 or uimm[4:0] as source - CSRSrcM = InstrM[14] ? {{(XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM; + CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM; // Compute AND/OR modification CSRRWM = CSRSrcM; CSRRSM = CSRReadValM | CSRSrcM; @@ -88,75 +88,20 @@ module csr #(parameter XLEN = 64, MISA = 0, ZCSR = 1, ZCOUNTERS = 1) ( // write CSRs assign CSRAdrM = InstrM[31:20]; assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM; - assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[XLEN-1:1], 1'b0} : {UnalignedNextEPCM[XLEN-1:2], 2'b00}; // 3.1.15 alignment + assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment assign NextCauseM = TrapM ? CauseM : CSRWriteValM; assign NextMtvalM = TrapM? NextFaultMtvalM : CSRWriteValM; assign CSRMWriteM = CSRWriteM && (PrivilegeModeW == `M_MODE); assign CSRSWriteM = CSRWriteM && (PrivilegeModeW[0]); assign CSRUWriteM = CSRWriteM; - csri #(XLEN, MISA) csri(.*); - csrsr #(XLEN, MISA) csrsr(.*); - csrc #(XLEN, ZCOUNTERS) counters(.*); - csrm #(XLEN, MISA) csrm(.*); // Machine Mode CSRs - csrs #(XLEN, MISA) csrs(.*); - csrn #(XLEN, MISA) csrn(.CSRNWriteM(CSRUWriteM), .*); // User Mode Exception Registers - csru #(XLEN, MISA) csru(.*); // Floating Point Flags are part of User MOde - -/* - - csri #(XLEN, MISA) csri( - clk, reset, CSRMWriteM, CSRSWriteM, CSRAdrM, ExtIntM, TimerIntM, SwIntM, - MIDELEG_REGW, MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, CSRWriteValM); - - csrsr #(XLEN, MISA) csrsr( - clk, reset, - WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM, TrapM, FloatRegWriteW, - NextPrivilegeModeM, PrivilegeModeW, - mretM, sretM, uretM, - CSRWriteValM, - MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW, - STATUS_MPP, STATUS_SPP, STATUS_TSR, STATUS_MIE, STATUS_SIE); - - csrc #(XLEN, ZCOUNTERS) counters( - clk, reset, - InstrValidW, LoadStallD, CSRMWriteM, CSRAdrM, PrivilegeModeW, CSRWriteValM, - MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW, - CSRCReadValM, IllegalCSRCAccessM); - - // Machine Mode CSRs - csrm #(XLEN, MISA) csrm( - clk, reset, - CSRMWriteM, MTrapM, CSRAdrM, - resetExceptionVector, - NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, - CSRWriteValM, CSRMReadValM, MEPC_REGW, MTVEC_REGW, MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, - MEDELEG_REGW, MIDELEG_REGW, MIP_REGW, MIE_REGW, WriteMIPM, WriteMIEM, WriteMSTATUSM, IllegalCSRMAccessM - ); - - csrs #(XLEN, MISA) csrs( - clk, reset, - CSRSWriteM, STrapM, CSRAdrM, - resetExceptionVector, - NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, - CSRWriteValM, CSRSReadValM, SEPC_REGW, STVEC_REGW, SCOUNTEREN_REGW, - SEDELEG_REGW, SIDELEG_REGW, SIP_REGW, SIE_REGW, WriteSIPM, WriteSIEM, WriteSSTATUSM, IllegalCSRSAccessM - ); - - csrn #(XLEN, MISA) csrn( // User Mode Exception Registers - clk, reset, - CSRUWriteM, UTrapM, CSRAdrM, - resetExceptionVector, - NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW, - CSRWriteValM, CSRNReadValM, UEPC_REGW, UTVEC_REGW, - UIP_REGW, UIE_REGW, WriteUIPM, WriteUIEM, WriteUSTATUSM, IllegalCSRNAccessM - ); - - csru #(XLEN, MISA) csru( // Floating Point Flags are part of User MOde - clk, reset, CSRUWriteM, CSRAdrM, - CSRWriteValM, CSRUReadValM, SetFflagsM, FRM_REGW, IllegalCSRUAccessM - ); - */ + csri csri(.*); + csrsr csrsr(.*); + csrc counters(.*); + csrm csrm(.*); // Machine Mode CSRs + csrs csrs(.*); + csrn csrn(.CSRNWriteM(CSRUWriteM), .*); // User Mode Exception Registers + csru csru(.*); // Floating Point Flags are part of User MOde // merge CSR Reads assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM; diff --git a/wally-pipelined/src/csrc.sv b/wally-pipelined/src/csrc.sv index f523d110d..db3bd44e3 100644 --- a/wally-pipelined/src/csrc.sv +++ b/wally-pipelined/src/csrc.sv @@ -24,9 +24,9 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module csrc #(parameter XLEN=64, ZCOUNTERS = 1, +module csrc #(parameter MCYCLE = 12'hB00, // MTIME = 12'hB01, // address not specified in privileged spec. Consider moving to CLINT to match SiFive // MTIMECMP = 12'hB21, // not specified in privileged spec. Move to CLINT @@ -67,9 +67,9 @@ module csrc #(parameter XLEN=64, ZCOUNTERS = 1, input logic InstrValidW, LoadStallD, CSRMWriteM, input logic [11:0] CSRAdrM, input logic [1:0] PrivilegeModeW, - input logic [XLEN-1:0] CSRWriteValM, + input logic [`XLEN-1:0] CSRWriteValM, input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW, - output logic [XLEN-1:0] CSRCReadValM, + output logic [`XLEN-1:0] CSRCReadValM, output logic IllegalCSRCAccessM ); @@ -80,9 +80,9 @@ module csrc #(parameter XLEN=64, ZCOUNTERS = 1, logic [63:0] HPMCOUNTER3_REGW, HPMCOUNTER4_REGW; // add more performance counters here if desired logic [63:0] CYCLEPlusM, TIMEPlusM, INSTRETPlusM; logic [63:0] HPMCOUNTER3PlusM, HPMCOUNTER4PlusM; - // logic [XLEN-1:0] NextTIMEM; - logic [XLEN-1:0] NextCYCLEM, NextINSTRETM; - logic [XLEN-1:0] NextHPMCOUNTER3M, NextHPMCOUNTER4M; + // logic [`XLEN-1:0] NextTIMEM; + logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM; + logic [`XLEN-1:0] NextHPMCOUNTER3M, NextHPMCOUNTER4M; logic WriteTIMEM, WriteTIMECMPM, WriteCYCLEM, WriteINSTRETM; logic WriteHPMCOUNTER3M, WriteHPMCOUNTER4M; logic [4:0] CounterNumM; @@ -101,15 +101,15 @@ module csrc #(parameter XLEN=64, ZCOUNTERS = 1, assign INSTRETPlusM = INSTRET_REGW + {63'b0, InstrValidW & ~MCOUNTINHIBIT_REGW[2]}; assign HPMCOUNTER3PlusM = HPMCOUNTER3_REGW + {63'b0, LoadStallD & ~MCOUNTINHIBIT_REGW[3]}; // count load stalls assign HPMCOUNTER4PlusM = HPMCOUNTER4_REGW + {63'b0, 1'b0 & ~MCOUNTINHIBIT_REGW[4]}; // change to count signals - assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[XLEN-1:0]; - // assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[XLEN-1:0]; - assign NextINSTRETM = WriteINSTRETM ? CSRWriteValM : INSTRETPlusM[XLEN-1:0]; - assign NextHPMCOUNTER3M = WriteHPMCOUNTER3M ? CSRWriteValM : HPMCOUNTER3PlusM[XLEN-1:0]; - assign NextHPMCOUNTER4M = WriteHPMCOUNTER4M ? CSRWriteValM : HPMCOUNTER4PlusM[XLEN-1:0]; + assign NextCYCLEM = WriteCYCLEM ? CSRWriteValM : CYCLEPlusM[`XLEN-1:0]; + // assign NextTIMEM = WriteTIMEM ? CSRWriteValM : TIMEPlusM[`XLEN-1:0]; + assign NextINSTRETM = WriteINSTRETM ? CSRWriteValM : INSTRETPlusM[`XLEN-1:0]; + assign NextHPMCOUNTER3M = WriteHPMCOUNTER3M ? CSRWriteValM : HPMCOUNTER3PlusM[`XLEN-1:0]; + assign NextHPMCOUNTER4M = WriteHPMCOUNTER4M ? CSRWriteValM : HPMCOUNTER4PlusM[`XLEN-1:0]; // Write / update counters // Only the Machine mode versions of the counter CSRs are writable - if (XLEN==64) begin// 64-bit counters + if (`XLEN==64) begin// 64-bit counters // flopr #(64) TIMEreg(clk, reset, WriteTIMEM ? CSRWriteValM : TIME_REGW + 1, TIME_REGW); // may count off a different clock*** // flopenr #(64) TIMECMPreg(clk, reset, WriteTIMECMPM, CSRWriteValM, TIMECMP_REGW); flopr #(64) CYCLEreg(clk, reset, NextCYCLEM, CYCLE_REGW); @@ -119,8 +119,8 @@ module csrc #(parameter XLEN=64, ZCOUNTERS = 1, end else begin // 32-bit low and high counters logic WriteTIMEHM, WriteTIMECMPHM, WriteCYCLEHM, WriteINSTRETHM; logic WriteHPMCOUNTER3HM, WriteHPMCOUNTER4HM; - logic [XLEN-1:0] NextCYCLEHM, NextTIMEHM, NextINSTRETHM; - logic [XLEN-1:0] NextHPMCOUNTER3HM, NextHPMCOUNTER4HM; + logic [`XLEN-1:0] NextCYCLEHM, NextTIMEHM, NextINSTRETHM; + logic [`XLEN-1:0] NextHPMCOUNTER3HM, NextHPMCOUNTER4HM; // Write Enables // assign WriteTIMEHM = CSRMWriteM && (CSRAdrM == MTIMEH); @@ -160,7 +160,7 @@ module csrc #(parameter XLEN=64, ZCOUNTERS = 1, // Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags assign CounterNumM = CSRAdrM[4:0]; // which counter to read? - if (XLEN==64) // 64-bit counter reads + if (`XLEN==64) // 64-bit counter reads always_comb if (PrivilegeModeW == `M_MODE || MCOUNTEREN_REGW[CounterNumM] && (PrivilegeModeW == `S_MODE || SCOUNTEREN_REGW[CounterNumM])) begin diff --git a/wally-pipelined/src/csri.sv b/wally-pipelined/src/csri.sv index 754480112..701dfa85e 100644 --- a/wally-pipelined/src/csri.sv +++ b/wally-pipelined/src/csri.sv @@ -24,9 +24,9 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module csri #(parameter XLEN=64, MISA=0, +module csri #(parameter // Machine CSRs MIE = 12'h304, MIP = 12'h344, @@ -36,15 +36,15 @@ module csri #(parameter XLEN=64, MISA=0, input logic CSRMWriteM, CSRSWriteM, input logic [11:0] CSRAdrM, input logic ExtIntM, TimerIntM, SwIntM, - input logic [XLEN-1:0] MIDELEG_REGW, + input logic [`XLEN-1:0] MIDELEG_REGW, output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, - input logic [XLEN-1:0] CSRWriteValM + input logic [`XLEN-1:0] CSRWriteValM ); logic [11:0] IntInM, IP_REGW, IE_REGW; logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK; logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM; - logic [XLEN-1:0] zero = 0; + logic [`XLEN-1:0] zero = 0; // Determine which interrupts need to be set // assumes no N-mode user interrupts diff --git a/wally-pipelined/src/csrm.sv b/wally-pipelined/src/csrm.sv index efb190e45..b4b4660ae 100644 --- a/wally-pipelined/src/csrm.sv +++ b/wally-pipelined/src/csrm.sv @@ -24,9 +24,9 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module csrm #(parameter XLEN=64, MISA=0, +module csrm #(parameter // Machine CSRs MVENDORID = 12'hF11, MARCHID = 12'hF12, @@ -64,30 +64,31 @@ module csrm #(parameter XLEN=64, MISA=0, input logic clk, reset, input logic CSRMWriteM, MTrapM, input logic [11:0] CSRAdrM, - input logic [XLEN-1:0] resetExceptionVector, - input logic [XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, - input logic [XLEN-1:0] CSRWriteValM, - output logic [XLEN-1:0] CSRMReadValM, MEPC_REGW, MTVEC_REGW, + input logic [`XLEN-1:0] resetExceptionVector, + input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, + input logic [`XLEN-1:0] CSRWriteValM, + output logic [`XLEN-1:0] CSRMReadValM, MEPC_REGW, MTVEC_REGW, output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, - output logic [XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, + output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, input logic [11:0] MIP_REGW, MIE_REGW, output logic WriteMIPM, WriteMIEM, output logic WriteMSTATUSM, output logic IllegalCSRMAccessM ); - logic [XLEN-1:0] MISA_REGW; - logic [XLEN-1:0] MSCRATCH_REGW,MCAUSE_REGW, MTVAL_REGW; - logic [XLEN-1:0] zero = 0; + logic [`XLEN-1:0] MISA_REGW; + logic [`XLEN-1:0] MSCRATCH_REGW,MCAUSE_REGW, MTVAL_REGW; + logic [`XLEN-1:0] zero = 0; logic [31:0] allones = {32{1'b1}}; - logic [XLEN-1:0] MEDELEG_MASK = ~(zero | 1'b1 << 11); // medeleg[11] hardwired to zero per Privileged Spec 3.1.8 - logic [XLEN-1:0] MIDELEG_MASK = {{(XLEN-12){1'b0}}, 12'h222}; // only allow delegating interrupts to supervisor mode + logic [`XLEN-1:0] MEDELEG_MASK = ~(zero | 1'b1 << 11); // medeleg[11] hardwired to zero per Privileged Spec 3.1.8 + logic [`XLEN-1:0] MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222}; // only allow delegating interrupts to supervisor mode logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM; logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM; logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM; + logic [25:0] MISAbits = `MISA; // MISA is hardwired. Spec says it could be written to disable features, but this is not supported by Wally - assign MISA_REGW = {(XLEN == 32 ? 2'b01 : 2'b10), {(XLEN-28){1'b0}}, MISA[25:0]}; + assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, MISAbits}; // Write machine Mode CSRs assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS); @@ -104,23 +105,23 @@ module csrm #(parameter XLEN=64, MISA=0, assign WriteMCOUNTINHIBITM = CSRMWriteM && (CSRAdrM == MCOUNTINHIBIT); // CSRs - flopenl #(XLEN) MTVECreg(clk, reset, WriteMTVECM, CSRWriteValM, resetExceptionVector, MTVEC_REGW); + flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, CSRWriteValM, resetExceptionVector, MTVEC_REGW); generate if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin // DELEG registers should exist - flopenl #(XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, zero, MEDELEG_REGW); - flopenl #(XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK, zero, MIDELEG_REGW); + flopenl #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, zero, MEDELEG_REGW); + flopenl #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK, zero, MIDELEG_REGW); end else begin assign MEDELEG_REGW = 0; assign MIDELEG_REGW = 0; end endgenerate -// flopenl #(XLEN) MIPreg(clk, reset, WriteMIPM, CSRWriteValM, zero, MIP_REGW); -// flopenl #(XLEN) MIEreg(clk, reset, WriteMIEM, CSRWriteValM, zero, MIE_REGW); - flopenr #(XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW); - flopenr #(XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); - flopenl #(XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, zero, MCAUSE_REGW); - flopenr #(XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW); +// flopenl #(`XLEN) MIPreg(clk, reset, WriteMIPM, CSRWriteValM, zero, MIP_REGW); +// flopenl #(`XLEN) MIEreg(clk, reset, WriteMIEM, CSRWriteValM, zero, MIE_REGW); + flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW); + flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); + flopenl #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, zero, MCAUSE_REGW); + flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW); flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], allones, MCOUNTEREN_REGW); flopenl #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], allones, MCOUNTINHIBIT_REGW); @@ -139,14 +140,14 @@ module csrm #(parameter XLEN=64, MISA=0, MTVEC: CSRMReadValM = MTVEC_REGW; MEDELEG: CSRMReadValM = MEDELEG_REGW; MIDELEG: CSRMReadValM = MIDELEG_REGW; - MIP: CSRMReadValM = {{(XLEN-12){1'b0}}, MIP_REGW}; - MIE: CSRMReadValM = {{(XLEN-12){1'b0}}, MIE_REGW}; + MIP: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW}; + MIE: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW}; MSCRATCH: CSRMReadValM = MSCRATCH_REGW; MEPC: CSRMReadValM = MEPC_REGW; MCAUSE: CSRMReadValM = MCAUSE_REGW; MTVAL: CSRMReadValM = MTVAL_REGW; - MCOUNTEREN:CSRMReadValM = {{(XLEN-32){1'b0}}, MCOUNTEREN_REGW}; - MCOUNTINHIBIT:CSRMReadValM = {{(XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW}; + MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW}; + MCOUNTINHIBIT:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW}; default: begin CSRMReadValM = 0; IllegalCSRMAccessM = 1; diff --git a/wally-pipelined/src/csrn.sv b/wally-pipelined/src/csrn.sv index 09c80c1d2..517f7cea7 100644 --- a/wally-pipelined/src/csrn.sv +++ b/wally-pipelined/src/csrn.sv @@ -24,9 +24,9 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module csrn #(parameter XLEN=64, MISA=0, +module csrn #(parameter USTATUS =12'h000, UIE = 12'h004, UTVEC = 12'h005, @@ -38,17 +38,17 @@ module csrn #(parameter XLEN=64, MISA=0, input logic clk, reset, input logic CSRNWriteM, UTrapM, input logic [11:0] CSRAdrM, - input logic [XLEN-1:0] resetExceptionVector, - input logic [XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW, - input logic [XLEN-1:0] CSRWriteValM, - output logic [XLEN-1:0] CSRNReadValM, UEPC_REGW, UTVEC_REGW, + input logic [`XLEN-1:0] resetExceptionVector, + input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW, + input logic [`XLEN-1:0] CSRWriteValM, + output logic [`XLEN-1:0] CSRNReadValM, UEPC_REGW, UTVEC_REGW, input logic [11:0] UIP_REGW, UIE_REGW, output logic WriteUIPM, WriteUIEM, output logic WriteUSTATUSM, output logic IllegalCSRNAccessM ); - logic [XLEN-1:0] zero = 0; + logic [`XLEN-1:0] zero = 0; // User mode CSRs below only needed when user mode traps are supported generate @@ -56,8 +56,8 @@ module csrn #(parameter XLEN=64, MISA=0, logic WriteUTVECM; logic WriteUSCRATCHM, WriteUEPCM; logic WriteUCAUSEM, WriteUTVALM; - logic [XLEN-1:0] UEDELEG_REGW, UIDELEG_REGW, UIP_REGW, UIE_REGW; - logic [XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW; + logic [`XLEN-1:0] UEDELEG_REGW, UIDELEG_REGW, UIP_REGW, UIE_REGW; + logic [`XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW; // Write enables assign WriteUSTATUSM = CSRNWriteM && (CSRAdrM == USTATUS); @@ -69,13 +69,13 @@ module csrn #(parameter XLEN=64, MISA=0, assign WriteUTVALM = UTrapM | (CSRNWriteM && (CSRAdrM == UTVAL)); // CSRs - flopenl #(XLEN) UTVECreg(clk, reset, WriteUTVECM, CSRWriteValM, resetExceptionVector, UTVEC_REGW); - // flopenl #(XLEN) UIPreg(clk, reset, WriteUIPM, CSRWriteValM, zero, UIP_REGW); - // flopenl #(XLEN) UIEreg(clk, reset, WriteUIEM, CSRWriteValM, zero, UIE_REGW); - flopenr #(XLEN) USCRATCHreg(clk, reset, WriteUSCRATCHM, CSRWriteValM, USCRATCH_REGW); - flopenr #(XLEN) UEPCreg(clk, reset, WriteUEPCM, NextEPCM, UEPC_REGW); - flopenr #(XLEN) UCAUSEreg(clk, reset, WriteUCAUSEM, NextCauseM, UCAUSE_REGW); - flopenr #(XLEN) UTVALreg(clk, reset, WriteUTVALM, NextMtvalM, UTVAL_REGW); + flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, CSRWriteValM, resetExceptionVector, UTVEC_REGW); + // flopenl #(`XLEN) UIPreg(clk, reset, WriteUIPM, CSRWriteValM, zero, UIP_REGW); + // flopenl #(`XLEN) UIEreg(clk, reset, WriteUIEM, CSRWriteValM, zero, UIE_REGW); + flopenr #(`XLEN) USCRATCHreg(clk, reset, WriteUSCRATCHM, CSRWriteValM, USCRATCH_REGW); + flopenr #(`XLEN) UEPCreg(clk, reset, WriteUEPCM, NextEPCM, UEPC_REGW); + flopenr #(`XLEN) UCAUSEreg(clk, reset, WriteUCAUSEM, NextCauseM, UCAUSE_REGW); + flopenr #(`XLEN) UTVALreg(clk, reset, WriteUTVALM, NextMtvalM, UTVAL_REGW); // CSR Reads always_comb begin @@ -83,8 +83,8 @@ module csrn #(parameter XLEN=64, MISA=0, case (CSRAdrM) USTATUS: CSRNReadValM = USTATUS_REGW; UTVEC: CSRNReadValM = UTVEC_REGW; - UIP: CSRNReadValM = {{(XLEN-12){1'b0}}, UIP_REGW}; - UIE: CSRNReadValM = {{(XLEN-12){1'b0}}, UIE_REGW}; + UIP: CSRNReadValM = {{(`XLEN-12){1'b0}}, UIP_REGW}; + UIE: CSRNReadValM = {{(`XLEN-12){1'b0}}, UIE_REGW}; USCRATCH: CSRNReadValM = USCRATCH_REGW; UEPC: CSRNReadValM = UEPC_REGW; UCAUSE: CSRNReadValM = UCAUSE_REGW; diff --git a/wally-pipelined/src/csrs.sv b/wally-pipelined/src/csrs.sv index 8f9c8be67..24ea77c6c 100644 --- a/wally-pipelined/src/csrs.sv +++ b/wally-pipelined/src/csrs.sv @@ -24,9 +24,9 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module csrs #(parameter XLEN=64, MISA=0, +module csrs #(parameter // Supervisor CSRs SSTATUS = 12'h100, SEDELEG = 12'h102, @@ -43,21 +43,21 @@ module csrs #(parameter XLEN=64, MISA=0, input logic clk, reset, input logic CSRSWriteM, STrapM, input logic [11:0] CSRAdrM, - input logic [XLEN-1:0] resetExceptionVector, - input logic [XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, - input logic [XLEN-1:0] CSRWriteValM, - output logic [XLEN-1:0] CSRSReadValM, SEPC_REGW, STVEC_REGW, + input logic [`XLEN-1:0] resetExceptionVector, + input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, + input logic [`XLEN-1:0] CSRWriteValM, + output logic [`XLEN-1:0] CSRSReadValM, SEPC_REGW, STVEC_REGW, output logic [31:0] SCOUNTEREN_REGW, - output logic [XLEN-1:0] SEDELEG_REGW, SIDELEG_REGW, + output logic [`XLEN-1:0] SEDELEG_REGW, SIDELEG_REGW, input logic [11:0] SIP_REGW, SIE_REGW, output logic WriteSIPM, WriteSIEM, output logic WriteSSTATUSM, output logic IllegalCSRSAccessM ); - logic [XLEN-1:0] zero = 0; + logic [`XLEN-1:0] zero = 0; logic [31:0] allones = {32{1'b1}}; - logic [XLEN-1:0] SEDELEG_MASK = ~(zero | 3'b111 << 9); // sedeleg[11:9] hardwired to zero per Privileged Spec 3.1.8 + logic [`XLEN-1:0] SEDELEG_MASK = ~(zero | 3'b111 << 9); // sedeleg[11:9] hardwired to zero per Privileged Spec 3.1.8 // Supervisor mode CSRs sometimes supported generate @@ -65,7 +65,7 @@ module csrs #(parameter XLEN=64, MISA=0, logic WriteSTVECM, WriteSEDELEGM, WriteSIDELEGM; logic WriteSSCRATCHM, WriteSEPCM; logic WriteSCAUSEM, WriteSTVALM, WriteSCOUNTERENM; - logic [XLEN-1:0] SSCRATCH_REGW, SCAUSE_REGW, STVAL_REGW; + logic [`XLEN-1:0] SSCRATCH_REGW, SCAUSE_REGW, STVAL_REGW; assign WriteSSTATUSM = CSRSWriteM && (CSRAdrM == SSTATUS); assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC); @@ -80,17 +80,17 @@ module csrs #(parameter XLEN=64, MISA=0, assign WriteSCOUNTERENM = CSRSWriteM && (CSRAdrM == SCOUNTEREN); // CSRs - flopenl #(XLEN) STVECreg(clk, reset, WriteSTVECM, CSRWriteValM, resetExceptionVector, STVEC_REGW); -// flopenl #(XLEN) SIPreg(clk, reset, WriteSIPM, CSRWriteValM, zero, SIP_REGW); -// flopenl #(XLEN) SIEreg(clk, reset, WriteSIEM, CSRWriteValM, zero, SIE_REGW); - flopenr #(XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW); - flopenr #(XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); - flopenl #(XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, zero, SCAUSE_REGW); - flopenr #(XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW); + flopenl #(`XLEN) STVECreg(clk, reset, WriteSTVECM, CSRWriteValM, resetExceptionVector, STVEC_REGW); +// flopenl #(`XLEN) SIPreg(clk, reset, WriteSIPM, CSRWriteValM, zero, SIP_REGW); +// flopenl #(`XLEN) SIEreg(clk, reset, WriteSIEM, CSRWriteValM, zero, SIE_REGW); + flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW); + flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW); + flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, zero, SCAUSE_REGW); + flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW); flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], allones, SCOUNTEREN_REGW); if (`N_SUPPORTED) begin - flopenl #(XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, zero, SEDELEG_REGW); - flopenl #(XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, zero, SIDELEG_REGW); + flopenl #(`XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, zero, SEDELEG_REGW); + flopenl #(`XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, zero, SIDELEG_REGW); end else begin assign SEDELEG_REGW = 0; assign SIDELEG_REGW = 0; @@ -104,13 +104,13 @@ module csrs #(parameter XLEN=64, MISA=0, STVEC: CSRSReadValM = STVEC_REGW; SEDELEG: CSRSReadValM = SEDELEG_REGW; SIDELEG: CSRSReadValM = SIDELEG_REGW; - SIP: CSRSReadValM = {{(XLEN-12){1'b0}}, SIP_REGW}; - SIE: CSRSReadValM = {{(XLEN-12){1'b0}}, SIE_REGW}; + SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, SIP_REGW}; + SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, SIE_REGW}; SSCRATCH: CSRSReadValM = SSCRATCH_REGW; SEPC: CSRSReadValM = SEPC_REGW; SCAUSE: CSRSReadValM = SCAUSE_REGW; STVAL: CSRSReadValM = STVAL_REGW; - SCOUNTEREN:CSRSReadValM = {{(XLEN-32){1'b0}}, SCOUNTEREN_REGW}; + SCOUNTEREN:CSRSReadValM = {{(`XLEN-32){1'b0}}, SCOUNTEREN_REGW}; default: begin CSRSReadValM = 0; IllegalCSRSAccessM = 1; diff --git a/wally-pipelined/src/csrsr.sv b/wally-pipelined/src/csrsr.sv index 6fde88838..bd356b674 100644 --- a/wally-pipelined/src/csrsr.sv +++ b/wally-pipelined/src/csrsr.sv @@ -24,15 +24,15 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module csrsr #(parameter XLEN=64, MISA = 0)( +module csrsr ( input logic clk, reset, input logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM, TrapM, FloatRegWriteW, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, input logic mretM, sretM, uretM, - input logic [XLEN-1:0] CSRWriteValM, - output logic [XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW, + input logic [`XLEN-1:0] CSRWriteValM, + output logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW, output logic [1:0] STATUS_MPP, output logic STATUS_SPP, STATUS_TSR, output logic STATUS_MIE, STATUS_SIE @@ -47,7 +47,7 @@ module csrsr #(parameter XLEN=64, MISA = 0)( // Lower privilege status registers are a subset of the full status register // *** consider adding MBE, SBE, UBE fields later from 20210108 draft spec generate - if (XLEN==64) begin// RV64 + if (`XLEN==64) begin// RV64 assign MSTATUS_REGW = {STATUS_SD, 27'b0, STATUS_SXL, STATUS_UXL, 9'b0, STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0, diff --git a/wally-pipelined/src/csru.sv b/wally-pipelined/src/csru.sv index bf91a79fc..802d0b82a 100644 --- a/wally-pipelined/src/csru.sv +++ b/wally-pipelined/src/csru.sv @@ -25,17 +25,17 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module csru #(parameter XLEN=64, MISA=0, +module csru #(parameter FFLAGS = 12'h001, FRM = 12'h002, FCSR = 12'h003) ( input logic clk, reset, input logic CSRUWriteM, input logic [11:0] CSRAdrM, - input logic [XLEN-1:0] CSRWriteValM, - output logic [XLEN-1:0] CSRUReadValM, + input logic [`XLEN-1:0] CSRWriteValM, + output logic [`XLEN-1:0] CSRUReadValM, input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, output logic IllegalCSRUAccessM @@ -66,9 +66,9 @@ module csru #(parameter XLEN=64, MISA=0, always_comb begin IllegalCSRUAccessM = 0; case (CSRAdrM) - FFLAGS: CSRUReadValM = {{(XLEN-5){1'b0}}, FFLAGS_REGW}; - FRM: CSRUReadValM = {{(XLEN-3){1'b0}}, FRM_REGW}; - FCSR: CSRUReadValM = {{(XLEN-8){1'b0}}, FRM_REGW, FFLAGS_REGW}; + FFLAGS: CSRUReadValM = {{(`XLEN-5){1'b0}}, FFLAGS_REGW}; + FRM: CSRUReadValM = {{(`XLEN-3){1'b0}}, FRM_REGW}; + FCSR: CSRUReadValM = {{(`XLEN-8){1'b0}}, FRM_REGW, FFLAGS_REGW}; default: begin CSRUReadValM = 0; IllegalCSRUAccessM = 1; diff --git a/wally-pipelined/src/datapath.sv b/wally-pipelined/src/datapath.sv index 06db69956..77b9b6f10 100644 --- a/wally-pipelined/src/datapath.sv +++ b/wally-pipelined/src/datapath.sv @@ -23,13 +23,13 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module datapath #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) ( +module datapath ( input logic clk, reset, // Fetch stage signals input logic StallF, - output logic [XLEN-1:0] PCF, + output logic [`XLEN-1:0] PCF, input logic [31:0] InstrF, // Decode stage signals output logic [6:0] OpD, @@ -55,8 +55,8 @@ module datapath #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) ( input logic TimerIntM, ExtIntM, SwIntM, output logic InstrMisalignedFaultM, input logic [2:0] Funct3M, - output logic [XLEN-1:0] WriteDataM, ALUResultM, - input logic [XLEN-1:0] ReadDataM, + output logic [`XLEN-1:0] WriteDataM, ALUResultM, + input logic [`XLEN-1:0] ReadDataM, output logic [7:0] ByteMaskM, output logic RetM, TrapM, input logic [4:0] SetFflagsM, @@ -73,51 +73,51 @@ module datapath #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) ( output logic [4:0] RdE, RdM, RdW); // Fetch stage signals - logic [XLEN-1:0] PCPlus2or4F; + logic [`XLEN-1:0] PCPlus2or4F; // Decode stage signals logic [31:0] InstrD; - logic [XLEN-1:0] PCD, PCPlus2or4D; - logic [XLEN-1:0] RD1D, RD2D; - logic [XLEN-1:0] ExtImmD; + logic [`XLEN-1:0] PCD, PCPlus2or4D; + logic [`XLEN-1:0] RD1D, RD2D; + logic [`XLEN-1:0] ExtImmD; logic [31:0] InstrDecompD; logic [4:0] RdD; // Execute stage signals logic [31:0] InstrE; - logic [XLEN-1:0] RD1E, RD2E; - logic [XLEN-1:0] PCE, ExtImmE; - logic [XLEN-1:0] PreSrcAE, SrcAE, SrcBE; - logic [XLEN-1:0] ALUResultE; - logic [XLEN-1:0] WriteDataE; - logic [XLEN-1:0] TargetBaseE; + logic [`XLEN-1:0] RD1E, RD2E; + logic [`XLEN-1:0] PCE, ExtImmE; + logic [`XLEN-1:0] PreSrcAE, SrcAE, SrcBE; + logic [`XLEN-1:0] ALUResultE; + logic [`XLEN-1:0] WriteDataE; + logic [`XLEN-1:0] TargetBaseE; // Memory stage signals logic [31:0] InstrM; - logic [XLEN-1:0] PCM; - logic [XLEN-1:0] SrcAM; - logic [XLEN-1:0] ReadDataExtM; - logic [XLEN-1:0] WriteDataFullM; - logic [XLEN-1:0] CSRReadValM; - logic [XLEN-1:0] PrivilegedNextPCM; + logic [`XLEN-1:0] PCM; + logic [`XLEN-1:0] SrcAM; + logic [`XLEN-1:0] ReadDataExtM; + logic [`XLEN-1:0] WriteDataFullM; + logic [`XLEN-1:0] CSRReadValM; + logic [`XLEN-1:0] PrivilegedNextPCM; logic LoadMisalignedFaultM, LoadAccessFaultM; logic StoreMisalignedFaultM, StoreAccessFaultM; - logic [XLEN-1:0] InstrMisalignedAdrM; + logic [`XLEN-1:0] InstrMisalignedAdrM; // Writeback stage signals - logic [XLEN-1:0] ALUResultW; - logic [XLEN-1:0] ReadDataW; - logic [XLEN-1:0] PCW; - logic [XLEN-1:0] CSRValW; - logic [XLEN-1:0] ResultW; + logic [`XLEN-1:0] ALUResultW; + logic [`XLEN-1:0] ReadDataW; + logic [`XLEN-1:0] PCW; + logic [`XLEN-1:0] CSRValW; + logic [`XLEN-1:0] ResultW; logic [31:0] nop = 32'h00000013; // instruction for NOP // Fetch stage pipeline register and logic; also Ex stage for branches - pclogic #(XLEN, MISA) pclogic(.*); + pclogic pclogic(.*); // Decode stage pipeline register and logic flopenl #(32) InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrD); - flopenrc #(XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD); - flopenrc #(XLEN) PCPlus2or4DReg(clk, reset, FlushD, ~StallD, PCPlus2or4F, PCPlus2or4D); + flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD); + flopenrc #(`XLEN) PCPlus2or4DReg(clk, reset, FlushD, ~StallD, PCPlus2or4F, PCPlus2or4D); - instrDecompress #(XLEN, MISA) decomp(.*); + instrDecompress decomp(.*); assign OpD = InstrDecompD[6:0]; assign Funct3D = InstrDecompD[14:12]; assign Funct7b5D = InstrDecompD[30]; @@ -125,45 +125,45 @@ module datapath #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) ( assign Rs2D = InstrDecompD[24:20]; assign RdD = InstrDecompD[11:7]; - regfile #(XLEN) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, RD1D, RD2D); - extend #(XLEN) ext(.InstrDecompD(InstrDecompD[31:7]), .*); + regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, RD1D, RD2D); + extend ext(.InstrDecompD(InstrDecompD[31:7]), .*); // Execute stage pipeline register and logic - floprc #(XLEN) RD1EReg(clk, reset, FlushE, RD1D, RD1E); - floprc #(XLEN) RD2EReg(clk, reset, FlushE, RD2D, RD2E); - floprc #(XLEN) PCEReg(clk, reset, FlushE, PCD, PCE); - floprc #(XLEN) ExtImmEReg(clk, reset, FlushE, ExtImmD, ExtImmE); + floprc #(`XLEN) RD1EReg(clk, reset, FlushE, RD1D, RD1E); + floprc #(`XLEN) RD2EReg(clk, reset, FlushE, RD2D, RD2E); + floprc #(`XLEN) PCEReg(clk, reset, FlushE, PCD, PCE); + floprc #(`XLEN) ExtImmEReg(clk, reset, FlushE, ExtImmD, ExtImmE); flopr #(32) InstrEReg(clk, reset, FlushE ? nop : InstrDecompD, InstrE); floprc #(5) Rs1EReg(clk, reset, FlushE, Rs1D, Rs1E); floprc #(5) Rs2EReg(clk, reset, FlushE, Rs2D, Rs2E); floprc #(5) RdEReg(clk, reset, FlushE, RdD, RdE); - mux3 #(XLEN) faemux(RD1E, ResultW, ALUResultM, ForwardAE, PreSrcAE); - mux3 #(XLEN) fbemux(RD2E, ResultW, ALUResultM, ForwardBE, WriteDataE); - mux2 #(XLEN) srcamux(PreSrcAE, PCE, ALUSrcAE, SrcAE); - mux2 #(XLEN) srcbmux(WriteDataE, ExtImmE, ALUSrcBE, SrcBE); - alu #(XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUResultE, FlagsE); - mux2 #(XLEN) targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE); + mux3 #(`XLEN) faemux(RD1E, ResultW, ALUResultM, ForwardAE, PreSrcAE); + mux3 #(`XLEN) fbemux(RD2E, ResultW, ALUResultM, ForwardBE, WriteDataE); + mux2 #(`XLEN) srcamux(PreSrcAE, PCE, ALUSrcAE, SrcAE); + mux2 #(`XLEN) srcbmux(WriteDataE, ExtImmE, ALUSrcBE, SrcBE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUResultE, FlagsE); + mux2 #(`XLEN) targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE); // Memory stage pipeline register - floprc #(XLEN) SrcAMReg(clk, reset, FlushM, SrcAE, SrcAM); - floprc #(XLEN) ALUResultMReg(clk, reset, FlushM, ALUResultE, ALUResultM); - floprc #(XLEN) WriteDataMReg(clk, reset, FlushM, WriteDataE, WriteDataFullM); - floprc #(XLEN) PCMReg(clk, reset, FlushM, PCE, PCM); + floprc #(`XLEN) SrcAMReg(clk, reset, FlushM, SrcAE, SrcAM); + floprc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ALUResultE, ALUResultM); + floprc #(`XLEN) WriteDataMReg(clk, reset, FlushM, WriteDataE, WriteDataFullM); + floprc #(`XLEN) PCMReg(clk, reset, FlushM, PCE, PCM); flopr #(32) InstrMReg(clk, reset, FlushM ? nop : InstrE, InstrM); floprc #(5) RdMEg(clk, reset, FlushM, RdE, RdM); - memdp #(XLEN) memdp(.AdrM(ALUResultM), .*); + memdp memdp(.AdrM(ALUResultM), .*); // Priveleged block operates in M and W stages, handling CSRs and exceptions - privileged #(XLEN, MISA, ZCSR, ZCOUNTERS) priv(.IllegalInstrFaultInM(IllegalInstrFaultM), .*); + privileged priv(.IllegalInstrFaultInM(IllegalInstrFaultM), .*); // Writeback stage pipeline register and logic - floprc #(XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW); - floprc #(XLEN) ReadDataWReg(clk, reset, FlushW, ReadDataExtM, ReadDataW); - floprc #(XLEN) PCWReg(clk, reset, FlushW, PCM, PCW); - floprc #(XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRValW); + floprc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW); + floprc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ReadDataExtM, ReadDataW); + floprc #(`XLEN) PCWReg(clk, reset, FlushW, PCM, PCW); + floprc #(`XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRValW); floprc #(5) RdWEg(clk, reset, FlushW, RdM, RdW); - mux4 #(XLEN) resultmux(ALUResultW, ReadDataW, PCW, CSRValW, ResultSrcW, ResultW); + mux4 #(`XLEN) resultmux(ALUResultW, ReadDataW, PCW, CSRValW, ResultSrcW, ResultW); endmodule diff --git a/wally-pipelined/src/dmem.sv b/wally-pipelined/src/dmem.sv index c6f02c9a9..2ff0ce50c 100644 --- a/wally-pipelined/src/dmem.sv +++ b/wally-pipelined/src/dmem.sv @@ -23,16 +23,16 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" // *** need idiom to map onto cache RAM with byte writes // *** and use memread signal to reduce power when reads aren't needed -module dmem #(parameter XLEN=32) ( +module dmem ( input logic clk, reset, input logic [1:0] MemRWM, input logic [7:0] ByteMaskM, - input logic [XLEN-1:0] AdrM, WriteDataM, - output logic [XLEN-1:0] ReadDataM, + input logic [`XLEN-1:0] AdrM, WriteDataM, + output logic [`XLEN-1:0] ReadDataM, output logic DataAccessFaultM, output logic TimerIntM, SwIntM, input logic [31:0] GPIOPinsIn, @@ -40,47 +40,47 @@ module dmem #(parameter XLEN=32) ( input logic UARTSin, output logic UARTSout); - logic [XLEN-1:0] MaskedWriteDataM; - logic [XLEN-1:0] RdTimM, RdCLINTM, RdGPIOM, RdUARTM; + logic [`XLEN-1:0] MaskedWriteDataM; + logic [`XLEN-1:0] RdTimM, RdCLINTM, RdGPIOM, RdUARTM; logic TimEnM, CLINTEnM, GPIOEnM, UARTEnM; logic [1:0] MemRWdtimM, MemRWclintM, MemRWgpioM; logic UARTIntr;// *** will need to tie INTR to an interrupt handler // Address decoding generate - if (XLEN == 64) - assign TimEnM = ~(|AdrM[XLEN-1:32]) & AdrM[31] & ~(|AdrM[30:19]); // 0x000...80000000 - 0x000...8007FFFF + if (`XLEN == 64) + assign TimEnM = ~(|AdrM[`XLEN-1:32]) & AdrM[31] & ~(|AdrM[30:19]); // 0x000...80000000 - 0x000...8007FFFF else assign TimEnM = AdrM[31] & ~(|AdrM[30:19]); // 0x80000000 - 0x8007FFFF endgenerate - assign CLINTEnM = ~(|AdrM[XLEN-1:26]) & AdrM[25] & ~(|AdrM[24:16]); // 0x02000000-0x0200FFFF + assign CLINTEnM = ~(|AdrM[`XLEN-1:26]) & AdrM[25] & ~(|AdrM[24:16]); // 0x02000000-0x0200FFFF assign GPIOEnM = (AdrM[31:8] == 24'h10012); // 0x10012000-0x100120FF - assign UARTEnM = ~(|AdrM[XLEN-1:29]) & AdrM[28] & ~(|AdrM[27:3]); // 0x10000000-0x10000007 + assign UARTEnM = ~(|AdrM[`XLEN-1:29]) & AdrM[28] & ~(|AdrM[27:3]); // 0x10000000-0x10000007 assign MemRWdtimM = MemRWM & {2{TimEnM}}; assign MemRWclintM = MemRWM & {2{CLINTEnM}}; assign MemRWgpioM = MemRWM & {2{GPIOEnM}}; // tightly integrated memory - dtim #(XLEN) dtim(.AdrM(AdrM[18:0]), .*); + dtim dtim(.AdrM(AdrM[18:0]), .*); // memory-mapped I/O peripherals - clint #(XLEN) clint(.AdrM(AdrM[15:0]), .*); - gpio #(XLEN) gpio(.AdrM(AdrM[7:0]), .*); // *** may want to add GPIO interrupts - uart #(XLEN) uart(.TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout), - .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), - .RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*); + clint clint(.AdrM(AdrM[15:0]), .*); + gpio gpio(.AdrM(AdrM[7:0]), .*); // *** may want to add GPIO interrupts + uart uart(.TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout), + .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), + .RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*); // *** add cache and interface to external memory & other peripherals // merge reads - assign ReadDataM = ({XLEN{TimEnM}} & RdTimM) | ({XLEN{CLINTEnM}} & RdCLINTM) | ({XLEN{GPIOEnM}} & RdGPIOM); + assign ReadDataM = ({`XLEN{TimEnM}} & RdTimM) | ({`XLEN{CLINTEnM}} & RdCLINTM) | ({`XLEN{GPIOEnM}} & RdGPIOM); assign DataAccessFaultM = ~(|TimEnM | CLINTEnM | GPIOEnM); // byte masking // write each byte based on the byte mask generate - if (XLEN==64) begin + if (`XLEN==64) begin always_comb begin MaskedWriteDataM=ReadDataM; if (ByteMaskM[0]) MaskedWriteDataM[7:0] = WriteDataM[7:0]; diff --git a/wally-pipelined/src/dtim.sv b/wally-pipelined/src/dtim.sv index 1a5d545d4..581c38789 100644 --- a/wally-pipelined/src/dtim.sv +++ b/wally-pipelined/src/dtim.sv @@ -23,18 +23,18 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module dtim #(parameter XLEN=32) ( +module dtim ( input logic clk, input logic [1:0] MemRWdtimM, input logic [7:0] ByteMaskM, input logic [18:0] AdrM, - input logic [XLEN-1:0] WriteDataM, - output logic [XLEN-1:0] RdTimM); + input logic [`XLEN-1:0] WriteDataM, + output logic [`XLEN-1:0] RdTimM); - logic [XLEN-1:0] RAM[0:65535]; - logic [XLEN-1:0] write; + logic [`XLEN-1:0] RAM[0:65535]; + logic [`XLEN-1:0] write; logic [15:0] entry; logic memread, memwrite; @@ -43,7 +43,7 @@ module dtim #(parameter XLEN=32) ( // word aligned reads generate - if (XLEN==64) + if (`XLEN==64) assign #2 entry = AdrM[18:3]; else assign #2 entry = AdrM[17:2]; @@ -56,7 +56,7 @@ module dtim #(parameter XLEN=32) ( // from dmem generate - if (XLEN==64) begin + if (`XLEN==64) begin always_comb begin write=RdTimM; if (ByteMaskM[0]) write[7:0] = WriteDataM[7:0]; diff --git a/wally-pipelined/src/extend.sv b/wally-pipelined/src/extend.sv index 9f2c5f90e..78a3d9734 100644 --- a/wally-pipelined/src/extend.sv +++ b/wally-pipelined/src/extend.sv @@ -23,25 +23,25 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module extend #(parameter XLEN=32) ( +module extend ( input logic [31:7] InstrDecompD, input logic [2:0] ImmSrcD, - output logic [XLEN-1:0] ExtImmD); + output logic [`XLEN-1:0] ExtImmD); always_comb case(ImmSrcD) // I-type - 3'b000: ExtImmD = {{(XLEN-12){InstrDecompD[31]}}, InstrDecompD[31:20]}; + 3'b000: ExtImmD = {{(`XLEN-12){InstrDecompD[31]}}, InstrDecompD[31:20]}; // S-type (stores) - 3'b001: ExtImmD = {{(XLEN-12){InstrDecompD[31]}}, InstrDecompD[31:25], InstrDecompD[11:7]}; + 3'b001: ExtImmD = {{(`XLEN-12){InstrDecompD[31]}}, InstrDecompD[31:25], InstrDecompD[11:7]}; // B-type (branches) - 3'b010: ExtImmD = {{(XLEN-12){InstrDecompD[31]}}, InstrDecompD[7], InstrDecompD[30:25], InstrDecompD[11:8], 1'b0}; + 3'b010: ExtImmD = {{(`XLEN-12){InstrDecompD[31]}}, InstrDecompD[7], InstrDecompD[30:25], InstrDecompD[11:8], 1'b0}; // J-type (jal) - 3'b011: ExtImmD = {{(XLEN-20){InstrDecompD[31]}}, InstrDecompD[19:12], InstrDecompD[20], InstrDecompD[30:21], 1'b0}; + 3'b011: ExtImmD = {{(`XLEN-20){InstrDecompD[31]}}, InstrDecompD[19:12], InstrDecompD[20], InstrDecompD[30:21], 1'b0}; // U-type (lui, auipc) - 3'b100: ExtImmD = {{(XLEN-31){InstrDecompD[31]}}, InstrDecompD[30:12], 12'b0}; + 3'b100: ExtImmD = {{(`XLEN-31){InstrDecompD[31]}}, InstrDecompD[30:12], 12'b0}; /* verilator lint_off WIDTH */ default: ExtImmD = 'bx; // undefined /* verilator lint_on WIDTH */ diff --git a/wally-pipelined/src/flop.sv b/wally-pipelined/src/flop.sv index 904ed6fd9..a76674621 100644 --- a/wally-pipelined/src/flop.sv +++ b/wally-pipelined/src/flop.sv @@ -23,7 +23,7 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" // ordinary flip-flop module flop #(parameter WIDTH = 8) ( diff --git a/wally-pipelined/src/gpio.sv b/wally-pipelined/src/gpio.sv index 8723cb98a..e1c35c3a6 100644 --- a/wally-pipelined/src/gpio.sv +++ b/wally-pipelined/src/gpio.sv @@ -25,15 +25,15 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module gpio #(parameter XLEN=32) ( +module gpio ( input logic clk, reset, input logic [1:0] MemRWgpioM, input logic [7:0] ByteMaskM, input logic [7:0] AdrM, - input logic [XLEN-1:0] MaskedWriteDataM, - output logic [XLEN-1:0] RdGPIOM, + input logic [`XLEN-1:0] MaskedWriteDataM, + output logic [`XLEN-1:0] RdGPIOM, input logic [31:0] GPIOPinsIn, output logic [31:0] GPIOPinsOut, GPIOPinsEn); @@ -47,7 +47,7 @@ module gpio #(parameter XLEN=32) ( // word aligned reads generate - if (XLEN==64) + if (`XLEN==64) assign #2 entry = {AdrM[7:3], 3'b000}; else assign #2 entry = {AdrM[7:2], 2'b00}; @@ -64,7 +64,7 @@ module gpio #(parameter XLEN=32) ( // register access generate - if (XLEN==64) begin + if (`XLEN==64) begin always_comb begin case(entry) 8'h00: RdGPIOM = {INPUT_EN, INPUT_VAL}; diff --git a/wally-pipelined/src/hazard.sv b/wally-pipelined/src/hazard.sv index 2a72b3db5..d454e5e0c 100644 --- a/wally-pipelined/src/hazard.sv +++ b/wally-pipelined/src/hazard.sv @@ -23,7 +23,7 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" module hazard( input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, diff --git a/wally-pipelined/src/imem.sv b/wally-pipelined/src/imem.sv index 6104b74fa..82bf83f23 100644 --- a/wally-pipelined/src/imem.sv +++ b/wally-pipelined/src/imem.sv @@ -23,19 +23,19 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module imem #(parameter XLEN=32) ( - input logic [XLEN-1:0] AdrF, +module imem ( + input logic [`XLEN-1:0] AdrF, output logic [31:0] InstrF, output logic InstrAccessFaultF); - logic [XLEN-1:0] RAM[0:65535]; + logic [`XLEN-1:0] RAM[0:65535]; logic [15:0] adrbits; - logic [XLEN-1:0] rd, rd2; + logic [`XLEN-1:0] rd, rd2; generate - if (XLEN==32) assign adrbits = AdrF[17:2]; + if (`XLEN==32) assign adrbits = AdrF[17:2]; else assign adrbits = AdrF[18:3]; endgenerate @@ -47,13 +47,13 @@ module imem #(parameter XLEN=32) ( // could be optimized to only stall when the instruction wrapping is 32 bits assign #2 rd2 = RAM[adrbits+1]; generate - if (XLEN==32) begin + if (`XLEN==32) begin assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd; assign InstrAccessFaultF = ~AdrF[31] | (|AdrF[30:16]); // memory mapped to 0x80000000-0x8000FFFF end else begin assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32]) : (AdrF[1] ? rd[47:16] : rd[31:0]); - assign InstrAccessFaultF = (|AdrF[XLEN-1:32]) | ~AdrF[31] | (|AdrF[30:16]); // memory mapped to 0x80000000-0x8000FFFF] + assign InstrAccessFaultF = (|AdrF[`XLEN-1:32]) | ~AdrF[31] | (|AdrF[30:16]); // memory mapped to 0x80000000-0x8000FFFF] end endgenerate endmodule diff --git a/wally-pipelined/src/instrDecompress.sv b/wally-pipelined/src/instrDecompress.sv index 51bf7024d..32fa4cd1a 100644 --- a/wally-pipelined/src/instrDecompress.sv +++ b/wally-pipelined/src/instrDecompress.sv @@ -23,9 +23,9 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module instrDecompress #(parameter XLEN=32, MISA=1) ( +module instrDecompress ( input logic [31:0] InstrD, output logic [31:0] InstrDecompD, output logic IllegalCompInstrD); @@ -89,18 +89,18 @@ module instrDecompress #(parameter XLEN=32, MISA=1) ( end 5'b00001: InstrDecompD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld 5'b00010: InstrDecompD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw - 5'b00011: if (XLEN==32) + 5'b00011: if (`XLEN==32) InstrDecompD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw else InstrDecompD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld; 5'b00101: InstrDecompD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd 5'b00110: InstrDecompD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw - 5'b00111: if (XLEN==32) + 5'b00111: if (`XLEN==32) InstrDecompD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw else InstrDecompD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd 5'b01000: InstrDecompD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi - 5'b01001: if (XLEN==32) + 5'b01001: if (`XLEN==32) InstrDecompD = {immCJ, 5'b00001, 7'b1101111}; // c.jal else InstrDecompD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw @@ -124,7 +124,7 @@ module instrDecompress #(parameter XLEN=32, MISA=1) ( InstrDecompD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or else // if (instr16[6:5] == 2'b11) InstrDecompD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and - else if (instr16[12:10] == 3'b111 && XLEN > 32) + else if (instr16[12:10] == 3'b111 && `XLEN > 32) if (instr16[6:5] == 2'b00) InstrDecompD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw else if (instr16[6:5] == 2'b01) @@ -143,7 +143,7 @@ module instrDecompress #(parameter XLEN=32, MISA=1) ( 5'b10000: InstrDecompD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli 5'b10001: InstrDecompD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp 5'b10010: InstrDecompD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp - 5'b10011: if (XLEN == 32) + 5'b10011: if (`XLEN == 32) InstrDecompD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp else InstrDecompD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp @@ -162,7 +162,7 @@ module instrDecompress #(parameter XLEN=32, MISA=1) ( InstrDecompD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add 5'b10101: InstrDecompD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp 5'b10110: InstrDecompD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp - 5'b10111: if (XLEN==32) + 5'b10111: if (`XLEN==32) InstrDecompD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp else InstrDecompD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp diff --git a/wally-pipelined/src/memdp.sv b/wally-pipelined/src/memdp.sv index 4dabdc85f..0b548e402 100644 --- a/wally-pipelined/src/memdp.sv +++ b/wally-pipelined/src/memdp.sv @@ -23,16 +23,16 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module memdp #(parameter XLEN=32) ( +module memdp ( input logic [1:0] MemRWM, - input logic [XLEN-1:0] ReadDataM, - input logic [XLEN-1:0] AdrM, + input logic [`XLEN-1:0] ReadDataM, + input logic [`XLEN-1:0] AdrM, input logic [2:0] Funct3M, - output logic [XLEN-1:0] ReadDataExtM, - input logic [XLEN-1:0] WriteDataFullM, - output logic [XLEN-1:0] WriteDataM, + output logic [`XLEN-1:0] ReadDataExtM, + input logic [`XLEN-1:0] WriteDataFullM, + output logic [`XLEN-1:0] WriteDataM, output logic [7:0] ByteMaskM, input logic DataAccessFaultM, output logic LoadMisalignedFaultM, LoadAccessFaultM, @@ -43,7 +43,7 @@ module memdp #(parameter XLEN=32) ( logic UnalignedM; generate - if (XLEN == 64) begin + if (`XLEN == 64) begin // bytMe mux always_comb case(AdrM[2:0]) diff --git a/wally-pipelined/src/mux.sv b/wally-pipelined/src/mux.sv index fbb5cc39d..acc07bb6b 100644 --- a/wally-pipelined/src/mux.sv +++ b/wally-pipelined/src/mux.sv @@ -23,7 +23,7 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" module mux2 #(parameter WIDTH = 8) ( diff --git a/wally-pipelined/src/pclogic.sv b/wally-pipelined/src/pclogic.sv index bc6af619b..290c00591 100644 --- a/wally-pipelined/src/pclogic.sv +++ b/wally-pipelined/src/pclogic.sv @@ -23,26 +23,26 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module pclogic #(parameter XLEN=64, MISA=0) ( +module pclogic ( input logic clk, reset, input logic StallF, PCSrcE, input logic [31:0] InstrF, - input logic [XLEN-1:0] ExtImmE, TargetBaseE, + input logic [`XLEN-1:0] ExtImmE, TargetBaseE, input logic RetM, TrapM, - input logic [XLEN-1:0] PrivilegedNextPCM, - output logic [XLEN-1:0] PCF, PCPlus2or4F, + input logic [`XLEN-1:0] PrivilegedNextPCM, + output logic [`XLEN-1:0] PCF, PCPlus2or4F, output logic InstrMisalignedFaultM, - output logic [XLEN-1:0] InstrMisalignedAdrM); + output logic [`XLEN-1:0] InstrMisalignedAdrM); - logic [XLEN-1:0] UnalignedPCNextF, PCNextF, PCTargetE; -// logic [XLEN-1:0] ResetVector = 'h100; -// logic [XLEN-1:0] ResetVector = 'he4; - logic [XLEN-1:0] ResetVector = {{(XLEN-32){1'b0}}, 32'h80000000}; + logic [`XLEN-1:0] UnalignedPCNextF, PCNextF, PCTargetE; +// logic [`XLEN-1:0] ResetVector = 'h100; +// logic [`XLEN-1:0] ResetVector = 'he4; + logic [`XLEN-1:0] ResetVector = {{(`XLEN-32){1'b0}}, 32'h80000000}; logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM; logic StallExceptResolveBranchesF, PrivilegedChangePCM; - logic [XLEN-3:0] PCPlusUpperF; + logic [`XLEN-3:0] PCPlusUpperF; logic CompressedF; assign PrivilegedChangePCM = RetM | TrapM; @@ -50,20 +50,20 @@ module pclogic #(parameter XLEN=64, MISA=0) ( assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM); assign PCTargetE = ExtImmE + TargetBaseE; - mux3 #(XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF); - assign PCNextF = {UnalignedPCNextF[XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment - flopenl #(XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, ResetVector, PCF); + mux3 #(`XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF); + assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment + flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, ResetVector, PCF); // pcadder // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32 assign CompressedF = (InstrF[1:0] != 2'b11); // is it a 16-bit compressed instruction? - assign PCPlusUpperF = PCF[XLEN-1:2] + 1; // add 4 to PC + assign PCPlusUpperF = PCF[`XLEN-1:2] + 1; // add 4 to PC // choose PC+2 or PC+4 always_comb if (CompressedF) // add 2 if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00}; - else PCPlus2or4F = {PCF[XLEN-1:2], 2'b10}; + else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10}; else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4 // Misaligned PC logic @@ -78,7 +78,7 @@ module pclogic #(parameter XLEN=64, MISA=0) ( // pipeline misaligned faults to M stage assign BranchMisalignedFaultE = misaligned & PCSrcE; // E-stage (Branch/Jump) misaligned flopr #(1) InstrMisalginedReg(clk, reset, BranchMisalignedFaultE, BranchMisalignedFaultM); - flopr #(XLEN) InstrMisalignedAdrReg(clk, reset, PCNextF, InstrMisalignedAdrM); + flopr #(`XLEN) InstrMisalignedAdrReg(clk, reset, PCNextF, InstrMisalignedAdrM); assign TrapMisalignedFaultM = misaligned & PrivilegedChangePCM; assign InstrMisalignedFaultM = BranchMisalignedFaultM; // | TrapMisalignedFaultM; *** put this back in without causing a cyclic path diff --git a/wally-pipelined/src/privilegeDecoder.sv b/wally-pipelined/src/privilegeDecoder.sv index 784bb749f..66041755a 100644 --- a/wally-pipelined/src/privilegeDecoder.sv +++ b/wally-pipelined/src/privilegeDecoder.sv @@ -24,9 +24,9 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module privilegeDecoder #(parameter MISA=0) ( +module privilegeDecoder ( input logic [31:20] InstrM, input logic PrivilegedM, IllegalInstrFaultInM, IllegalCSRAccessM, input logic [1:0] PrivilegeModeW, diff --git a/wally-pipelined/src/privilegeModeReg.sv b/wally-pipelined/src/privilegeModeReg.sv index ae4cd04c2..cd16db1b8 100644 --- a/wally-pipelined/src/privilegeModeReg.sv +++ b/wally-pipelined/src/privilegeModeReg.sv @@ -24,20 +24,20 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module privilegeModeReg #(parameter XLEN=32, MISA=0) ( +module privilegeModeReg ( input logic clk, reset, input logic mretM, sretM, uretM, TrapM, input logic [1:0] STATUS_MPP, input logic STATUS_SPP, - input logic [XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, CauseM, + input logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, CauseM, output logic [1:0] NextPrivilegeModeM, PrivilegeModeW); logic md, sd; // get bits of DELEG registers based on CAUSE - assign md = CauseM[XLEN-1] ? MIDELEG_REGW[CauseM[4:0]] : MEDELEG_REGW[CauseM[4:0]]; - assign sd = CauseM[XLEN-1] ? SIDELEG_REGW[CauseM[4:0]] : SEDELEG_REGW[CauseM[4:0]]; // depricated + assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[4:0]] : MEDELEG_REGW[CauseM[4:0]]; + assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[4:0]] : SEDELEG_REGW[CauseM[4:0]]; // depricated always_comb if (reset) NextPrivilegeModeM = `M_MODE; // Privilege resets to 11 (Machine Mode) diff --git a/wally-pipelined/src/privileged.sv b/wally-pipelined/src/privileged.sv index 8d0cbc299..607e472ed 100644 --- a/wally-pipelined/src/privileged.sv +++ b/wally-pipelined/src/privileged.sv @@ -24,16 +24,16 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module privileged #(parameter XLEN=32, MISA = 0, ZCSR = 1, ZCOUNTERS = 1)( +module privileged ( input logic clk, reset, input logic CSRWriteM, - input logic [XLEN-1:0] SrcAM, + input logic [`XLEN-1:0] SrcAM, input logic [31:0] InstrM, - input logic [XLEN-1:0] PCM, - output logic [XLEN-1:0] CSRReadValM, - output logic [XLEN-1:0] PrivilegedNextPCM, + input logic [`XLEN-1:0] PCM, + output logic [`XLEN-1:0] CSRReadValM, + output logic [`XLEN-1:0] PrivilegedNextPCM, output logic RetM, TrapM, input logic InstrValidW, FloatRegWriteW, LoadStallD, input logic PrivilegedM, @@ -41,16 +41,16 @@ module privileged #(parameter XLEN=32, MISA = 0, ZCSR = 1, ZCOUNTERS = 1)( input logic LoadMisalignedFaultM, LoadAccessFaultM, input logic StoreMisalignedFaultM, StoreAccessFaultM, input logic TimerIntM, ExtIntM, SwIntM, - input logic [XLEN-1:0] InstrMisalignedAdrM, ALUResultM, + input logic [`XLEN-1:0] InstrMisalignedAdrM, ALUResultM, input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW ); logic [1:0] NextPrivilegeModeM, PrivilegeModeW; - logic [XLEN-1:0] CauseM, NextFaultMtvalM; - logic [XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW; - logic [XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW; + logic [`XLEN-1:0] CauseM, NextFaultMtvalM; + logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW; + logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW; // logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW; logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM; @@ -66,10 +66,10 @@ module privileged #(parameter XLEN=32, MISA = 0, ZCSR = 1, ZCOUNTERS = 1)( logic [11:0] MIP_REGW, MIE_REGW; // track the current privilege level - privilegeModeReg #(XLEN, MISA) pmr (.*); + privilegeModeReg pmr(.*); // decode privileged instructions - privilegeDecoder #(MISA) pmd(.InstrM(InstrM[31:20]), .*); + privilegeDecoder pmd(.InstrM(InstrM[31:20]), .*); // Extract exceptions by name and handle them assign BreakpointFaultM = ebreakM; // could have other causes too @@ -77,10 +77,10 @@ module privileged #(parameter XLEN=32, MISA = 0, ZCSR = 1, ZCOUNTERS = 1)( assign InstrPageFaultM = 0; assign LoadPageFaultM = 0; assign StorePageFaultM = 0; - trap #(XLEN, MISA) trap(.*); + trap trap(.*); // Control and Status Registers - csr #(XLEN, MISA, ZCSR, ZCOUNTERS) csr(.*); + csr csr(.*); endmodule diff --git a/wally-pipelined/src/regfile.sv b/wally-pipelined/src/regfile.sv index 738683efd..0374ba4c9 100644 --- a/wally-pipelined/src/regfile.sv +++ b/wally-pipelined/src/regfile.sv @@ -23,16 +23,16 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module regfile #(parameter XLEN=32) ( +module regfile ( input logic clk, reset, input logic we3, input logic [ 4:0] a1, a2, a3, - input logic [XLEN-1:0] wd3, - output logic [XLEN-1:0] rd1, rd2); + input logic [`XLEN-1:0] wd3, + output logic [`XLEN-1:0] rd1, rd2); - logic [XLEN-1:0] rf[31:1]; + logic [`XLEN-1:0] rf[31:1]; integer i; // three ported register file diff --git a/wally-pipelined/src/shifter.sv b/wally-pipelined/src/shifter.sv index 374584c7b..2e28c7db4 100644 --- a/wally-pipelined/src/shifter.sv +++ b/wally-pipelined/src/shifter.sv @@ -23,7 +23,7 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" module shifter #(parameter WIDTH=32) ( input logic [WIDTH-1:0] a, @@ -31,7 +31,7 @@ module shifter #(parameter WIDTH=32) ( input logic right, arith, w64, output logic [WIDTH-1:0] y); - // The best shifter architecture differs based on XLEN. + // The best shifter architecture differs based on `XLEN. // for RV32, only 32-bit shifts are needed. These are // most efficiently implemented with a funnel shifter. // For RV64, 32 and 64-bit shifts are needed, with sign diff --git a/wally-pipelined/src/testbench.sv b/wally-pipelined/src/testbench.sv index 2fbc678aa..2ec3d0878 100644 --- a/wally-pipelined/src/testbench.sv +++ b/wally-pipelined/src/testbench.sv @@ -23,22 +23,22 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module testbench #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOUNTERS = 1)(); +module testbench(); logic clk; logic reset; - logic [XLEN-1:0] WriteData, DataAdr; + logic [`XLEN-1:0] WriteData, DataAdr; logic [1:0] MemRW; int test, i, errors, totalerrors; logic [31:0] sig32[0:10000]; - logic [XLEN-1:0] signature[0:10000]; - logic [XLEN-1:0] testadr; + logic [`XLEN-1:0] signature[0:10000]; + logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; - logic [XLEN-1:0] meminit; + logic [`XLEN-1:0] meminit; string tests64ic[] = '{ "rv64ic/I-C-ADD-01", "3000", @@ -224,7 +224,7 @@ string tests32i[] = { // pick tests based on modes supported initial - if (XLEN == 64) begin // RV64 + if (`XLEN == 64) begin // RV64 tests = {tests64i}; if (`C_SUPPORTED % 2 == 1) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; @@ -240,13 +240,13 @@ string tests32i[] = { // instantiate device to be tested assign GPIOPinsIn = 0; - wallypipelined #(XLEN, MISA, ZCSR, ZCOUNTERS) dut( + wallypipelined dut( clk, reset, WriteData, DataAdr, MemRW, GPIOPinsIn, GPIOPinsOut, GPIOPinsEn, UARTSin, UARTSout ); // Track names of instructions - instrTrackerTB #(XLEN) it(clk, reset, dut.hart.dp.FlushE, + instrTrackerTB it(clk, reset, dut.hart.dp.FlushE, dut.hart.dp.InstrDecompD, dut.hart.dp.InstrE, dut.hart.dp.InstrM, InstrW, InstrDName, InstrEName, InstrMName, InstrWName); @@ -258,7 +258,7 @@ string tests32i[] = { totalerrors = 0; testadr = 0; // fill memory with defined values to reduce Xs in simulation - if (XLEN == 32) meminit = 32'hFEDC0123; + if (`XLEN == 32) meminit = 32'hFEDC0123; else meminit = 64'hFEDCBA9876543210; for (i=0; i<=65535; i = i+1) begin //dut.imem.RAM[i] = meminit; @@ -294,7 +294,7 @@ string tests32i[] = { $readmemh(signame, sig32); i = 0; while (i < 10000) begin - if (XLEN == 32) begin + if (`XLEN == 32) begin signature[i] = sig32[i]; i = i+1; end else begin @@ -306,7 +306,7 @@ string tests32i[] = { // Check errors i = 0; errors = 0; - if (XLEN == 32) + if (`XLEN == 32) testadr = tests[test+1].atohex()/4; else testadr = tests[test+1].atohex()/8; @@ -319,7 +319,7 @@ string tests32i[] = { // kind of hacky test for garbage right now errors = errors+1; $display(" Error on test %s result %d: adr = %h sim = %h, signature = %h", - tests[test], i, (testadr+i)*XLEN/8, dut.dmem.dtim.RAM[testadr+i], signature[i]); + tests[test], i, (testadr+i)*`XLEN/8, dut.dmem.dtim.RAM[testadr+i], signature[i]); end end i = i + 1; @@ -350,7 +350,7 @@ endmodule /* verilator lint_on STMTDLY */ /* verilator lint_on WIDTH */ -module instrTrackerTB #(parameter XLEN=32) ( +module instrTrackerTB( input logic clk, reset, FlushE, input logic [31:0] InstrD, input logic [31:0] InstrE, InstrM, diff --git a/wally-pipelined/src/trap.sv b/wally-pipelined/src/trap.sv index 6bffecbf8..6c3039ebf 100644 --- a/wally-pipelined/src/trap.sv +++ b/wally-pipelined/src/trap.sv @@ -24,9 +24,9 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module trap #(parameter XLEN=32, MISA=0) ( +module trap ( input logic clk, reset, input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM, input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM, @@ -34,13 +34,13 @@ module trap #(parameter XLEN=32, MISA=0) ( input logic LoadPageFaultM, StorePageFaultM, input logic mretM, sretM, uretM, input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, - input logic [XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, + input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW, input logic [11:0] MIP_REGW, MIE_REGW, input logic STATUS_MIE, STATUS_SIE, - input logic [XLEN-1:0] InstrMisalignedAdrM, ALUResultM, + input logic [`XLEN-1:0] InstrMisalignedAdrM, ALUResultM, input logic [31:0] InstrM, output logic TrapM, MTrapM, STrapM, UTrapM, RetM, - output logic [XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM + output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM // output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, // input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM ); @@ -76,18 +76,18 @@ module trap #(parameter XLEN=32, MISA=0) ( // Exceptions are of lower priority than all interrupts (3.1.9) always_comb if (reset) CauseM = 0; // hard reset 3.3 - else if (PendingIntsM[11]) CauseM = (1 << (XLEN-1)) + 11; // Machine External Int - else if (PendingIntsM[3]) CauseM = (1 << (XLEN-1)) + 3; // Machine Sw Int - else if (PendingIntsM[7]) CauseM = (1 << (XLEN-1)) + 7; // Machine Timer Int - else if (PendingIntsM[9]) CauseM = (1 << (XLEN-1)) + 9; // Supervisor External Int - else if (PendingIntsM[1]) CauseM = (1 << (XLEN-1)) + 1; // Supervisor Sw Int - else if (PendingIntsM[5]) CauseM = (1 << (XLEN-1)) + 5; // Supervisor Timer Int + else if (PendingIntsM[11]) CauseM = (1 << (`XLEN-1)) + 11; // Machine External Int + else if (PendingIntsM[3]) CauseM = (1 << (`XLEN-1)) + 3; // Machine Sw Int + else if (PendingIntsM[7]) CauseM = (1 << (`XLEN-1)) + 7; // Machine Timer Int + else if (PendingIntsM[9]) CauseM = (1 << (`XLEN-1)) + 9; // Supervisor External Int + else if (PendingIntsM[1]) CauseM = (1 << (`XLEN-1)) + 1; // Supervisor Sw Int + else if (PendingIntsM[5]) CauseM = (1 << (`XLEN-1)) + 5; // Supervisor Timer Int else if (InstrPageFaultM) CauseM = 12; else if (InstrAccessFaultM) CauseM = 1; else if (InstrMisalignedFaultM) CauseM = 0; else if (IllegalInstrFaultM) CauseM = 2; else if (BreakpointFaultM) CauseM = 3; - else if (EcallFaultM) CauseM = {{(XLEN-2){1'b0}}, PrivilegeModeW} + 8; + else if (EcallFaultM) CauseM = {{(`XLEN-2){1'b0}}, PrivilegeModeW} + 8; else if (LoadMisalignedFaultM) CauseM = 4; else if (StoreMisalignedFaultM) CauseM = 6; else if (LoadPageFaultM) CauseM = 13; @@ -112,6 +112,6 @@ module trap #(parameter XLEN=32, MISA=0) ( else if (InstrPageFaultM) NextFaultMtvalM = 0; // *** implement else if (LoadPageFaultM) NextFaultMtvalM = ALUResultM; else if (StorePageFaultM) NextFaultMtvalM = ALUResultM; - else if (IllegalInstrFaultM) NextFaultMtvalM = {{(XLEN-32){1'b0}}, InstrM}; + else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; else NextFaultMtvalM = 0; endmodule \ No newline at end of file diff --git a/wally-pipelined/src/uart.sv b/wally-pipelined/src/uart.sv index 31e001dbb..ed041c7e5 100644 --- a/wally-pipelined/src/uart.sv +++ b/wally-pipelined/src/uart.sv @@ -25,15 +25,15 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module uart #(parameter XLEN=32) ( +module uart ( input logic clk, reset, input logic [1:0] MemRWgpioM, input logic [7:0] ByteMaskM, - input logic [XLEN-1:0] AdrM, - input logic [XLEN-1:0] MaskedWriteDataM, - output logic [XLEN-1:0] RdUARTM, + input logic [`XLEN-1:0] AdrM, + input logic [`XLEN-1:0] MaskedWriteDataM, + output logic [`XLEN-1:0] RdUARTM, input logic SIN, DSRb, DCDb, CTSb, RIb, // from E1A driver from RS232 interface output logic SOUT, RTSb, DTRb, // to E1A driver to RS232 interface output logic OUT1b, OUT2b, INTR, TXRDYb, RXRDYb); // to CPU @@ -50,7 +50,7 @@ module uart #(parameter XLEN=32) ( assign A = AdrM[2:0]; generate - if (XLEN == 64) begin + if (`XLEN == 64) begin always_comb begin /* RdUARTM = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout}; case (AdrM[2:0]) diff --git a/wally-pipelined/src/uartPC16550D.sv b/wally-pipelined/src/uartPC16550D.sv index 62037cc62..59251e854 100644 --- a/wally-pipelined/src/uartPC16550D.sv +++ b/wally-pipelined/src/uartPC16550D.sv @@ -29,7 +29,7 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" module uartPC16550D( // Processor Interface diff --git a/wally-pipelined/src/wally-config.vh b/wally-pipelined/src/wally-config.vh new file mode 100644 index 000000000..baa035bd2 --- /dev/null +++ b/wally-pipelined/src/wally-config.vh @@ -0,0 +1,67 @@ +////////////////////////////////////////// +// wally-config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// RV32 or RV64: XLEN = 32 or 64 +`define XLEN 64 + +`define MISA (32'h00000104) +`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) +`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) +`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) +`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) +`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) +`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) +`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) +`define ZCSR_SUPPORTED 1 +`define ZCOUNTERS_SUPPORTED 1 +// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 +//`define N_SUPPORTED ((MISA >> 13) % 2 == 1) +`define N_SUPPORTED 0 + +`define M_MODE (2'b11) +`define S_MODE (2'b01) +`define U_MODE (2'b00) + +// Microarchitectural Features +`define UARCH_PIPELINED 1 +`define UARCH_SUPERSCALR 0 +`define UARCH_SINGLECYCLE 0 +`define MEM_DCACHE 0 +`define MEM_DTIM 1 +`define MEM_ICACHE 0 +`define MEM_VIRTMEM 0 + +// Test modes + +// Tie GPIO outputs back to inputs +`define GPIO_LOOPBACK_TEST 0 + + +// Hardware configuration +`define UART_PRESCALE 1 + +/* verilator lint_off STMTDLY */ +/* verilator lint_off WIDTH */ diff --git a/wally-pipelined/src/wallypipelined.sv b/wally-pipelined/src/wallypipelined.sv index bec09fd6b..9fe936809 100644 --- a/wally-pipelined/src/wallypipelined.sv +++ b/wally-pipelined/src/wallypipelined.sv @@ -50,11 +50,11 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module wallypipelined #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) ( +module wallypipelined ( input logic clk, reset, - output logic [XLEN-1:0] WriteDataM, DataAdrM, + output logic [`XLEN-1:0] WriteDataM, DataAdrM, output logic [1:0] MemRWM, input logic [31:0] GPIOPinsIn, output logic [31:0] GPIOPinsOut, GPIOPinsEn, @@ -62,7 +62,7 @@ module wallypipelined #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) ( output logic UARTSout ); - logic [XLEN-1:0] PCF, ReadDataM; + logic [`XLEN-1:0] PCF, ReadDataM; logic [31:0] InstrF; logic [7:0] ByteMaskM; logic InstrAccessFaultF, DataAccessFaultM; @@ -70,8 +70,8 @@ module wallypipelined #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) ( logic ExtIntM = 0; // not yet connected // instantiate processor and memories - wallypipelinedhart #(XLEN, MISA, ZCSR, ZCOUNTERS) hart(.ALUResultM(DataAdrM), .*); + wallypipelinedhart hart(.ALUResultM(DataAdrM), .*); - imem #(XLEN) imem(.AdrF(PCF), .*); - dmem #(XLEN) dmem(.AdrM(DataAdrM), .*); + imem imem(.AdrF(PCF), .*); + dmem dmem(.AdrM(DataAdrM), .*); endmodule \ No newline at end of file diff --git a/wally-pipelined/src/wallypipelinedhart.sv b/wally-pipelined/src/wallypipelinedhart.sv index 482051bcc..25702a84a 100644 --- a/wally-pipelined/src/wallypipelinedhart.sv +++ b/wally-pipelined/src/wallypipelinedhart.sv @@ -23,16 +23,16 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-macros.sv" +`include "wally-config.vh" -module wallypipelinedhart #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) ( +module wallypipelinedhart ( input logic clk, reset, - output logic [XLEN-1:0] PCF, + output logic [`XLEN-1:0] PCF, input logic [31:0] InstrF, output logic [1:0] MemRWM, output logic [7:0] ByteMaskM, - output logic [XLEN-1:0] ALUResultM, WriteDataM, - input logic [XLEN-1:0] ReadDataM, + output logic [`XLEN-1:0] ALUResultM, WriteDataM, + input logic [`XLEN-1:0] ReadDataM, input logic TimerIntM, ExtIntM, SwIntM, input logic InstrAccessFaultF, input logic DataAccessFaultM); @@ -70,8 +70,8 @@ module wallypipelinedhart #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) logic FloatRegWriteW; controller c(.*); - datapath #(XLEN, MISA, ZCSR, ZCOUNTERS) dp(.*); - hazard hz(.*); + datapath dp(.*); + hazard hz(.*); // add FPU here, with SetFflagsM, FRM_REGW // presently stub out SetFlagsM and FloatRegWriteW