diff --git a/wally-pipelined/src/dcu/dcu.sv b/wally-pipelined/src/dmem/dmem.sv
similarity index 95%
rename from wally-pipelined/src/dcu/dcu.sv
rename to wally-pipelined/src/dmem/dmem.sv
index e6f01bd49..65e6dcdf9 100644
--- a/wally-pipelined/src/dcu/dcu.sv
+++ b/wally-pipelined/src/dmem/dmem.sv
@@ -1,12 +1,12 @@
 ///////////////////////////////////////////
-// dcu.sv
+// dmem.sv
 //
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: Data cache unit
+// Purpose: Data memory
 //          Top level of the memory-stage hart logic
-//          Contains data cache, subword read/write datapath, interface to external bus
+//          Contains data cache, DTLB, subword read/write datapath, interface to external bus
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -27,7 +27,7 @@
 
 `include "wally-config.vh"
 
-module dcu (
+module dmem (
   input  logic [1:0]      MemRWM,
   output logic [1:0]      MemRWdcuoutM,
   output logic            DataMisalignedM,
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 685d2ac19..4dc5f959c 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -93,7 +93,7 @@ module wallypipelinedhart (
   ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache
 
   ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller
-  dcu dcu(/*.Funct3M(InstrM[14:12]),*/ .*); // data cache unit
+  dmem dmem(/*.Funct3M(InstrM[14:12]),*/ .*); // data cache unit
 
   ahblite ebu( // *** make IRData InstrF
     .IPAdrF(PCF), .IReadF(1'b1), .IRData(), //.IReady(),