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Before returning to the ready state the dcache must set SelAdr = 0 on the cycle before.

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This commit is contained in:
Ross Thompson 2021-07-17 17:56:40 -05:00
parent e3bf8db80b
commit 053e9593af
1 changed files with 9 additions and 3 deletions
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12
wally-pipelined/src/cache/dcache.sv vendored
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@ -149,6 +149,7 @@ module dcache
STATE_MISS_READ_WORD,
STATE_MISS_READ_WORD_DELAY,
STATE_MISS_WRITE_WORD,
STATE_MISS_WRITE_WORD_DELAY,
STATE_AMO_MISS_FETCH_WDV,
STATE_AMO_MISS_FETCH_DONE,
@ -315,7 +316,7 @@ module dcache
assign CPUBusy = CurrState == STATE_CPU_BUSY;
flop #(1) CPUBusyReg(.clk, .d(CPUBusy), .q(PreviousCPUBusy));
assign ReadDataWEn = (~StallW & ~PreviousCPUBusy) |
assign ReadDataWEn = (~StallW & (~PreviousCPUBusy & (CurrState != STATE_CPU_BUSY))) |
(NextState == STATE_CPU_BUSY & CurrState == STATE_READY) |
(CurrState == STATE_MISS_READ_WORD_DELAY);
@ -573,7 +574,7 @@ module dcache
end
STATE_MISS_READ_WORD_DELAY: begin
SelAdrM = 1'b1;
//SelAdrM = 1'b1;
CommittedM = 1'b1;
if(StallW) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;
@ -583,7 +584,12 @@ module dcache
SRAMWordWriteEnableM = 1'b1;
SetDirtyM = 1'b1;
SelAdrM = 1'b1;
DCacheStall = 1'b0;
DCacheStall = 1'b1;
CommittedM = 1'b1;
NextState = STATE_MISS_WRITE_WORD_DELAY;
end
STATE_MISS_WRITE_WORD_DELAY: begin
CommittedM = 1'b1;
if(StallW) NextState = STATE_CPU_BUSY;
else NextState = STATE_READY;