From f758a53247872bcf8bb1882f99d933fb738b90f4 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 12 Dec 2021 17:31:39 -0600
Subject: [PATCH 1/2] Revert "Priviledged .* removed"
This reverts commit a95efea0b34f219c420e9ff7f6b613a0869ba791.
---
wally-pipelined/src/privileged/privileged.sv | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 3cb7a1833..512364e6e 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -22,7 +22,7 @@
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-// SOFTWARE.
+ SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
From 395766219bf3cc426d299b14caae7268bb39b4f9 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 12 Dec 2021 17:31:57 -0600
Subject: [PATCH 2/2] Revert "Privilige .*s removed"
This reverts commit 82bab8e90e485c687a8fb7679a73b9c16160e14b.
---
addins/riscv-arch-test | 2 +-
wally-pipelined/src/privileged/privileged.sv | 69 +++-----------------
2 files changed, 11 insertions(+), 60 deletions(-)
diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index 84d043817..be67c99bd 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit 84d043817f75f752c9873326475e11f16e3a6f7c
+Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 512364e6e..a6c3f2d8f 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -21,8 +21,7 @@
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
@@ -85,7 +84,7 @@ module privileged (
logic [`XLEN-1:0] CauseM, NextFaultMtvalM;
logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW;
- // logic [11:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
+// logic [11:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM;
@@ -112,8 +111,8 @@ module privileged (
///////////////////////////////////////////
// get bits of DELEG registers based on CAUSE
- // assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[3:0]];
- // assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[3:0]] : SEDELEG_REGW[CauseM[3:0]]; // depricated
+// assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[3:0]];
+// assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[3:0]] : SEDELEG_REGW[CauseM[3:0]]; // depricated
assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[`LOG_XLEN-1:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]];
assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[`LOG_XLEN-1:0]] : SEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; // depricated
@@ -144,44 +143,15 @@ module privileged (
///////////////////////////////////////////
// decode privileged instructions
-
-
///////////////////////////////////////////
-
- privdec pmd(.InstrM(InstrM[31:20]),
- .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM,
- .PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM,
- .uretM, .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM);
+
+ privdec pmd(.InstrM(InstrM[31:20]), .*);
///////////////////////////////////////////
// Control and Status Registers
///////////////////////////////////////////
-
- csr csr(.clk,. reset,
- .FlushE, .FlushM, .FlushW,
- .StallE, .StallM, .StallW,
- .InstrM, .PCM, .SrcAM,
- .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .uretM,
- .TimerIntM, .ExtIntM, .SwIntM,
- .MTIME_CLINT, .MTIMECMP_CLINT,
- .InstrValidM, .FRegWriteM, .LoadStallD,
- .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
- .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess,
- .NextPrivilegeModeM, .PrivilegeModeW,
- .CauseM, .NextFaultMtvalM, .STATUS_MPP,
- .STATUS_SPP, .STATUS_TSR,
- .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
- .MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW,
- .SATP_REGW,
- .MIP_REGW, .MIE_REGW, .SIP_REGW, S.IE_REGW,
- .STATUS_MIE, .STATUS_SIE,
- .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW,
- .PMPCFG_ARRAY_REGW,
- .PMPADDR_ARRAY_REGW,
- .SetFflagsM,
- .FRM_REGW,
- .CSRReadValW,
- .IllegalCSRAccessM);
+
+ csr csr(.*);
///////////////////////////////////////////
// Extract exceptions by name and handle them
@@ -218,28 +188,9 @@ module privileged (
flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM,
{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
- // *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
-
- trap trap(.clk, .reset,
- .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
- .BreakpointFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM,
- .LoadAccessFaultM, .StoreAccessFaultM, .EcallFaultM, .InstrPageFaultM,
- .LoadPageFaultM, .StorePageFaultM,
- .mretM, .sretM, .uretM,
- .PrivilegeModeW, .NextPrivilegeModeM
- .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
- .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,
- .STATUS_MIE, .STATUS_SIE
- .PCM,
- .InstrMisalignedAdrM, .MemAdrM,
- .InstrM,
- .InstrValidM, .CommittedM,
- .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
- .InterruptM,
- .ExceptionM,
- .PendingInterruptM,
- .PrivilegedNextPCM, .CauseM, .NextFaultMtvalM);
+ // *** it should be possible to compbine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
+ trap trap(.*);
endmodule