Modifying tracer toward being able to run non-gc configurations in lockstep

testbench/common/wallyTracer.sv

@@ -95,11 +95,19 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   assign FlushW         = testbench.dut.core.FlushW;
   assign TrapM          = testbench.dut.core.TrapM;
   assign HaltM          = testbench.DCacheFlushStart;
+  if (P.ZICSR_SUPPORTED) begin
     assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW;
     assign STATUS_SXL     = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL;
     assign STATUS_UXL     = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
     assign wfiM           = testbench.dut.core.priv.priv.wfiM;
     assign InterruptM     = testbench.dut.core.priv.priv.InterruptM;
+  end else begin
+    assign PrivilegeModeW = 2'b11;
+    assign STATUS_SXL     = 0;
+    assign STATUS_UXL     = 0;
+    assign wfiM           = 0;
+    assign InterruptM     = 0;
+  end
 
   //For VM Verification
   assign VAdrIM         = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
@@ -116,6 +124,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
 
   logic valid;
   
+  if (P.ZICSR_SUPPORTED) begin
     always_comb begin
       // Since we are detected the CSR change by comparing the old value we need to
       // ensure the CSR is detected when the pipeline's Writeback stage is not
@@ -292,6 +301,9 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
         end
       end    
     end
+  end else begin
+    // no CSRArray
+  end
 
   genvar index;
   assign rf[0] = 0;
@@ -307,11 +319,18 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
       rf_wb[rf_a3] <= 1'b1;
   end
 
-  for(index = 0; index < NUMREGS; index += 1) 
+  if (P.F_SUPPORTED) begin
-  assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
-  
     assign frf_a4  = testbench.dut.core.fpu.fpu.fregfile.a4;
     assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4;
+    for(index = 0; index < NUMREGS; index += 1) 
+      assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
+  end else begin
+    assign frf_a4  = '0;
+    assign frf_we4 = 0;
+    for(index = 0; index < NUMREGS; index += 1) 
+      assign frf[index] = '0;
+  end
+  
   
   always_comb begin
     frf_wb <= 0;

testbench/testbench.sv

@@ -866,12 +866,14 @@ end
 
   end
 
+  if (P.ZICSR_SUPPORTED) begin
     always @(dut.core.priv.priv.csr.csri.MIP_REGW[7])   void'(rvvi.net_push("MTimerInterrupt",    dut.core.priv.priv.csr.csri.MIP_REGW[7]));
     always @(dut.core.priv.priv.csr.csri.MIP_REGW[11])  void'(rvvi.net_push("MExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[11]));
     always @(dut.core.priv.priv.csr.csri.MIP_REGW[9])   void'(rvvi.net_push("SExternalInterrupt", dut.core.priv.priv.csr.csri.MIP_REGW[9]));
     always @(dut.core.priv.priv.csr.csri.MIP_REGW[3])   void'(rvvi.net_push("MSWInterrupt",       dut.core.priv.priv.csr.csri.MIP_REGW[3]));
     always @(dut.core.priv.priv.csr.csri.MIP_REGW[1])   void'(rvvi.net_push("SSWInterrupt",       dut.core.priv.priv.csr.csri.MIP_REGW[1]));
     always @(dut.core.priv.priv.csr.csri.MIP_REGW[5])   void'(rvvi.net_push("STimerInterrupt",    dut.core.priv.priv.csr.csri.MIP_REGW[5]));
+  end
 
   final begin
     void'(rvviRefShutdown());