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Ross Thompson 2023-03-24 15:15:38 -05:00
parent 1ff15c3882
commit 0511c73e22
6 changed files with 98 additions and 107 deletions
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22
src/cache/cache.sv vendored
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@ -98,9 +98,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
logic CacheEn; logic CacheEn;
logic [CACHEWORDSPERLINE-1:0] MemPAdrDecoded; logic [CACHEWORDSPERLINE-1:0] MemPAdrDecoded;
logic [LINELEN/8-1:0] LineByteMask, DemuxedByteMask, FetchBufferByteSel; logic [LINELEN/8-1:0] LineByteMask, DemuxedByteMask, FetchBufferByteSel;
logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr; logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
genvar index; genvar index;
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Read Path // Read Path
@ -154,9 +154,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
// Bus address for fetch, writeback, or flush writeback // Bus address for fetch, writeback, or flush writeback
mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
.d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}),
.d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}), .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}),
.s({SelFlush, SelWriteback}), .y(CacheBusAdr)); .s({SelFlush, SelWriteback}), .y(CacheBusAdr));
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Write Path // Write Path
@ -198,11 +198,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
cachefsm #(READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, cachefsm #(READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
.FlushStage, .CacheRW, .CacheAtomic, .Stall, .FlushStage, .CacheRW, .CacheAtomic, .Stall,
.CacheHit, .LineDirty, .CacheStall, .CacheCommitted, .CacheHit, .LineDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdr, .CacheMiss, .CacheAccess, .SelAdr,
.ClearValid, .ClearDirty, .SetDirty, .SetValid, .SelWriteback, .SelFlush, .ClearValid, .ClearDirty, .SetDirty, .SetValid, .SelWriteback, .SelFlush,
.FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst, .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
.FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,
.InvalidateCache, .CacheEn, .LRUWriteEn); .InvalidateCache, .CacheEn, .LRUWriteEn);
endmodule endmodule

76
src/cache/cachefsm.sv vendored
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@ -47,7 +47,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
output logic [1:0] CacheBusRW, // [1] Read (cache line fetch) or [0] write bus (cache line writeback) output logic [1:0] CacheBusRW, // [1] Read (cache line fetch) or [0] write bus (cache line writeback)
// performance counter outputs // performance counter outputs
output logic CacheMiss, // Cache miss output logic CacheMiss, // Cache miss
output logic CacheAccess, // Cache access output logic CacheAccess, // Cache access
// cache internals // cache internals
input logic CacheHit, // Exactly 1 way hits input logic CacheHit, // Exactly 1 way hits
@ -69,21 +69,21 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
output logic CacheEn // Enable the cache memory arrays. Disable hold read data constant output logic CacheEn // Enable the cache memory arrays. Disable hold read data constant
); );
logic resetDelay; logic resetDelay;
logic AMO, StoreAMO; logic AMO, StoreAMO;
logic AnyUpdateHit, AnyHit; logic AnyUpdateHit, AnyHit;
logic AnyMiss; logic AnyMiss;
logic FlushFlag; logic FlushFlag;
typedef enum logic [3:0]{STATE_READY, // hit states typedef enum logic [3:0]{STATE_READY, // hit states
// miss states // miss states
STATE_FETCH, STATE_FETCH,
STATE_WRITEBACK, STATE_WRITEBACK,
STATE_WRITE_LINE, STATE_WRITE_LINE,
STATE_READ_HOLD, // required for back to back reads. structural hazard on writting SRAM STATE_READ_HOLD, // required for back to back reads. structural hazard on writting SRAM
// flush cache // flush cache
STATE_FLUSH, STATE_FLUSH,
STATE_FLUSH_WRITEBACK} statetype; STATE_FLUSH_WRITEBACK} statetype;
statetype CurrState, NextState; statetype CurrState, NextState;
@ -111,26 +111,26 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
always_comb begin always_comb begin
NextState = STATE_READY; NextState = STATE_READY;
case (CurrState) case (CurrState)
STATE_READY: if(InvalidateCache) NextState = STATE_READY; STATE_READY: if(InvalidateCache) NextState = STATE_READY;
else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH;
else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH;
else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK; else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK;
else NextState = STATE_READY; else NextState = STATE_READY;
STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE;
else NextState = STATE_FETCH; else NextState = STATE_FETCH;
STATE_WRITE_LINE: NextState = STATE_READ_HOLD; STATE_WRITE_LINE: NextState = STATE_READ_HOLD;
STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD;
else NextState = STATE_READY; else NextState = STATE_READY;
STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH; STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH;
else NextState = STATE_WRITEBACK; else NextState = STATE_WRITEBACK;
// eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK; STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK;
else if (FlushFlag) NextState = STATE_READ_HOLD; else if (FlushFlag) NextState = STATE_READ_HOLD;
else NextState = STATE_FLUSH; else NextState = STATE_FLUSH;
STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH; STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH;
else if(CacheBusAck) NextState = STATE_READ_HOLD; else if(CacheBusAck) NextState = STATE_READ_HOLD;
else NextState = STATE_FLUSH_WRITEBACK; else NextState = STATE_FLUSH_WRITEBACK;
default: NextState = STATE_READY; default: NextState = STATE_READY;
endcase endcase
end end
@ -156,14 +156,14 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
(CurrState == STATE_READY & AnyMiss & LineDirty); (CurrState == STATE_READY & AnyMiss & LineDirty);
assign SelFlush = (CurrState == STATE_READY & FlushCache) | assign SelFlush = (CurrState == STATE_READY & FlushCache) |
(CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH) |
(CurrState == STATE_FLUSH_WRITEBACK); (CurrState == STATE_FLUSH_WRITEBACK);
assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) | assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) |
(CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty); (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty);
assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) | assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) |
(CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck); (CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck);
assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) | assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) |
(CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck); (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck);
// Bus interface controls // Bus interface controls
assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) |
(CurrState == STATE_FETCH & ~CacheBusAck) | (CurrState == STATE_FETCH & ~CacheBusAck) |

14
src/cache/cacheway.sv vendored
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@ -30,7 +30,7 @@
`include "wally-config.vh" `include "wally-config.vh"
module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) ( OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) (
input logic clk, input logic clk,
input logic reset, input logic reset,
input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations) input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations)
@ -86,8 +86,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
assign SelNonHit = FlushWayEn | SetValid | SelWriteback; assign SelNonHit = FlushWayEn | SetValid | SelWriteback;
mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag); mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
//assign SelTag = VictimWay | FlushWay;
//assign SelData = HitWay | FlushWayEn | VictimWayEn;
mux2 #(1) selectedwaymux(HitWay, SelTag, SelNonHit , SelData); mux2 #(1) selectedwaymux(HitWay, SelTag, SelNonHit , SelData);
@ -95,10 +93,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
// Write Enable demux // Write Enable demux
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// RT: Can we merge these two muxes? This is also shared in cacheLRU.
//mux3 #(1) selectwaymux(HitWay, VictimWay, FlushWay, {SelFlush, SetValid}, SelData);
//mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelNonHit}, SelData);
assign SetValidWay = SetValid & SelData; assign SetValidWay = SetValid & SelData;
assign ClearValidWay = ClearValid & SelData; assign ClearValidWay = ClearValid & SelData;
assign SetDirtyWay = SetDirty & SelData; assign SetDirtyWay = SetDirty & SelData;
@ -117,8 +111,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
.addr(CacheSet), .dout(ReadTag), .bwe('1), .addr(CacheSet), .dout(ReadTag), .bwe('1),
.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN)); .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
// AND portion of distributed tag multiplexer // AND portion of distributed tag multiplexer
assign TagWay = SelTag ? ReadTag : '0; // AND part of AOMux assign TagWay = SelTag ? ReadTag : '0; // AND part of AOMux
assign DirtyWay = SelTag & Dirty & ValidWay; assign DirtyWay = SelTag & Dirty & ValidWay;
@ -152,8 +144,8 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
always_ff @(posedge clk) begin // Valid bit array, always_ff @(posedge clk) begin // Valid bit array,
if (reset) ValidBits <= #1 '0; if (reset) ValidBits <= #1 '0;
if(CacheEn) begin if(CacheEn) begin
ValidWay <= #1 ValidBits[CacheSet]; ValidWay <= #1 ValidBits[CacheSet];
if(InvalidateCache) ValidBits <= #1 '0; if(InvalidateCache) ValidBits <= #1 '0;
else if (SetValidEN | (ClearValidWay & ~FlushStage)) ValidBits[CacheSet] <= #1 SetValidWay; else if (SetValidEN | (ClearValidWay & ~FlushStage)) ValidBits[CacheSet] <= #1 SetValidWay;
end end
end end

6
src/cache/subcachelineread.sv vendored
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@ -33,8 +33,8 @@ module subcachelineread #(parameter LINELEN, WORDLEN,
parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$ parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$
input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address
input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline
output logic [WORDLEN-1:0] ReadDataWord // read data of selected word. output logic [WORDLEN-1:0] ReadDataWord // read data of selected word.
); );
localparam WORDSPERLINE = LINELEN/MUXINTERVAL; localparam WORDSPERLINE = LINELEN/MUXINTERVAL;
@ -50,7 +50,7 @@ module subcachelineread #(parameter LINELEN, WORDLEN,
genvar index; genvar index;
for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux
assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1 : (index*MUXINTERVAL)]; assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1 : (index*MUXINTERVAL)];
end end
// variable input mux // variable input mux

42
src/ebu/buscachefsm.sv
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@ -35,33 +35,33 @@ module buscachefsm #(
parameter BeatCountThreshold, // Largest beat index parameter BeatCountThreshold, // Largest beat index
parameter AHBWLOGBWPL // Log2 of BEATSPERLINE parameter AHBWLOGBWPL // Log2 of BEATSPERLINE
)( )(
input logic HCLK, input logic HCLK,
input logic HRESETn, input logic HRESETn,
// IEU interface // IEU interface
input logic Stall, // Core pipeline is stalled input logic Stall, // Core pipeline is stalled
input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write
output logic BusStall, // Bus is busy with an in flight memory operation output logic BusStall, // Bus is busy with an in flight memory operation
output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
// ahb cache interface locals. // ahb cache interface locals.
output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA
// cache interface // cache interface
input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
output logic CacheBusAck, // Handshack to $ indicating bus transaction completed output logic CacheBusAck, // Handshack to $ indicating bus transaction completed
// lsu interface // lsu interface
output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase
output logic [AHBWLOGBWPL-1:0] BeatCountDelayed, // Beat within the cache line in the second (Data) cache stage output logic [AHBWLOGBWPL-1:0] BeatCountDelayed, // Beat within the cache line in the second (Data) cache stage
output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
// BUS interface // BUS interface
input logic HREADY, // AHB peripheral ready input logic HREADY, // AHB peripheral ready
output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
output logic HWRITE, // AHB 0: Read operation 1: Write operation output logic HWRITE, // AHB 0: Read operation 1: Write operation
output logic [2:0] HBURST // AHB burst length output logic [2:0] HBURST // AHB burst length
); );
typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype; typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype;
@ -70,11 +70,11 @@ module buscachefsm #(
busstatetype CurrState, NextState; busstatetype CurrState, NextState;
logic [AHBWLOGBWPL-1:0] NextBeatCount; logic [AHBWLOGBWPL-1:0] NextBeatCount;
logic FinalBeatCount; logic FinalBeatCount;
logic [2:0] LocalBurstType; logic [2:0] LocalBurstType;
logic BeatCntEn; logic BeatCntEn;
logic BeatCntReset; logic BeatCntReset;
logic CacheAccess; logic CacheAccess;
always_ff @(posedge HCLK) always_ff @(posedge HCLK)
if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
@ -144,7 +144,7 @@ module buscachefsm #(
// communication to cache // communication to cache
assign CacheBusAck = (CacheAccess & HREADY & FinalBeatCount); assign CacheBusAck = (CacheAccess & HREADY & FinalBeatCount);
assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) | assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) |
(CurrState == DATA_PHASE & BusRW[0]) | (CurrState == DATA_PHASE & BusRW[0]) |
(CurrState == CACHE_WRITEBACK) | (CurrState == CACHE_WRITEBACK) |
(CurrState == CACHE_FETCH); (CurrState == CACHE_FETCH);

37
src/ebu/ebu.sv
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@ -52,27 +52,26 @@ module ebu (
output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority
// AHB-Lite external signals // AHB-Lite external signals
output logic HCLK, HRESETn, output logic HCLK, HRESETn,
input logic HREADY, // AHB peripheral ready input logic HREADY, // AHB peripheral ready
input logic HRESP, // AHB peripheral response. 0: OK 1: Error input logic HRESP, // AHB peripheral response. 0: OK 1: Error
output logic [`PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration output logic [`PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration
output logic [`AHBW-1:0] HWDATA, // AHB Write data after arbitration output logic [`AHBW-1:0] HWDATA, // AHB Write data after arbitration
output logic [`XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration output logic [`XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration
output logic HWRITE, // AHB transaction direction after arbitration output logic HWRITE, // AHB transaction direction after arbitration
output logic [2:0] HSIZE, // AHB transaction size after arbitration output logic [2:0] HSIZE, // AHB transaction size after arbitration
output logic [2:0] HBURST, // AHB burst length after arbitration output logic [2:0] HBURST, // AHB burst length after arbitration
output logic [3:0] HPROT, // AHB protection. Wally does not use output logic [3:0] HPROT, // AHB protection. Wally does not use
output logic [1:0] HTRANS, // AHB transaction request after arbitration output logic [1:0] HTRANS, // AHB transaction request after arbitration
output logic HMASTLOCK // AHB master lock. Wally does not use output logic HMASTLOCK // AHB master lock. Wally does not use
); );
logic LSUDisable; logic LSUDisable;
logic LSUSelect; logic LSUSelect;
logic IFUSave; logic IFUSave;
logic IFURestore; logic IFURestore;
logic IFUDisable; logic IFUDisable;
logic IFUSelect; logic IFUSelect;
logic [`PA_BITS-1:0] IFUHADDROut; logic [`PA_BITS-1:0] IFUHADDROut;
logic [1:0] IFUHTRANSOut; logic [1:0] IFUHTRANSOut;
@ -87,7 +86,7 @@ module ebu (
logic LSUHWRITEOut; logic LSUHWRITEOut;
logic IFUReq; logic IFUReq;
logic LSUReq; logic LSUReq;
assign HCLK = clk; assign HCLK = clk;
assign HRESETn = ~reset; assign HRESETn = ~reset;
@ -127,7 +126,7 @@ module ebu (
// HRDATA is sent to all controllers at the core level. // HRDATA is sent to all controllers at the core level.
ebufsmarb ebufsmarb(.HCLK, .HRESETn, .HBURST, .HREADY, .LSUReq, .IFUReq, .IFUSave, ebufsmarb ebufsmarb(.HCLK, .HRESETn, .HBURST, .HREADY, .LSUReq, .IFUReq, .IFUSave,
.IFURestore, .IFUDisable, .IFUSelect, .LSUDisable, .LSUSelect); .IFURestore, .IFUDisable, .IFUSelect, .LSUDisable, .LSUSelect);
endmodule endmodule