From 0505f1fd379dd6f85cf8835f55772418d5d966c1 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 23 Dec 2022 00:27:44 -0800
Subject: [PATCH] Moved InstrValidNotFLushed to csr including InstrValidM

---
 pipelined/src/privileged/csr.sv  | 6 +++---
 pipelined/src/privileged/csrc.sv | 5 ++---
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv
index 0932bcc74..35e17495d 100644
--- a/pipelined/src/privileged/csr.sv
+++ b/pipelined/src/privileged/csr.sv
@@ -106,7 +106,7 @@ module csr #(parameter
   logic [`XLEN-1:0] TVecAlignedM;
   
   logic InstrValidNotFlushedM;
-  assign InstrValidNotFlushedM = ~StallW & ~FlushW;
+  assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
 
   ///////////////////////////////////////////
   // MTVAL
@@ -212,8 +212,8 @@ module csr #(parameter
               .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM,
               .STATUS_FS, .BigEndianM);
   csrc  counters(.clk, .reset,
-              .StallE, .StallM, .StallW, .FlushM, .FlushW,   
-              .InstrValidM, .LoadStallD, .CSRMWriteM,
+              .StallE, .StallM, .StallW, .FlushM,
+              .InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
               .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
               .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
               .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv
index dbb6af756..5efa3ec00 100644
--- a/pipelined/src/privileged/csrc.sv
+++ b/pipelined/src/privileged/csrc.sv
@@ -43,8 +43,8 @@ module csrc #(parameter
 ) (
     input logic 	     clk, reset,
     input logic 	     StallE, StallM, StallW,
-    input logic        FlushM, FlushW,   
-    input logic 	     InstrValidM, LoadStallD, CSRMWriteM,
+    input logic        FlushM, 
+    input logic 	     InstrValidNotFlushedM, LoadStallD, CSRMWriteM,
     input logic 	     BPPredDirWrongM,
     input logic 	     BTBPredPCWrongM,
     input logic 	     RASPredPCWrongM,
@@ -78,7 +78,6 @@ module csrc #(parameter
     // Interface signals
     flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE));  // don't flush the load stall during a load stall.
     flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));	
-    assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
     
     // Determine when to increment each counter
     assign CounterEvent[0] = 1'b1;  // MCYCLE always increments