Yes. The hack to not repeat the d memory operation fixed this issue.

wally-pipelined/regression/wave.do

@@ -101,6 +101,9 @@ add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
 add wave -noupdate /testbench/InstrFName
+add wave -noupdate -expand -group {dcache memory} /testbench/dut/hart/dmem/MemReadM
+add wave -noupdate -expand -group {dcache memory} /testbench/dut/hart/dmem/MemWriteM
+add wave -noupdate -expand -group {dcache memory} /testbench/dut/hart/dmem/MemAckW
 add wave -noupdate -group dcache /testbench/dut/hart/MemAdrM
 add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM
 add wave -noupdate -group dcache /testbench/dut/hart/WriteDataM
@@ -174,6 +177,8 @@ add wave -noupdate -expand -group icache -expand -group {fsm out and control} /t
 add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PCMux
 add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
 add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
 add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBByteLength
 add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/AHBOFFETWIDTH
 add wave -noupdate -expand -group icache -group parameters /testbench/dut/hart/ifu/icache/controller/BlockByteLength
@@ -219,8 +224,24 @@ add wave -noupdate /testbench/dut/hart/ifu/icache/cachemem/OldReadPAdr
 add wave -noupdate /testbench/dut/hart/ifu/CompressedF
 add wave -noupdate /testbench/dut/hart/ifu/icache/controller/SpillDataBlock0
 add wave -noupdate /testbench/dut/hart/ifu/icache/controller/PCPreFinalF_q
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/BusState
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HCLK
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HRDATA
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HREADY
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HRESP
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HADDR
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWDATA
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITE
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZE
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HBURST
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HPROT
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HTRANS
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HMASTLOCK
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HADDRD
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HSIZED
+add wave -noupdate -expand -group AHB /testbench/dut/hart/ebu/HWRITED
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 2} {9808584 ns} 0} {{Cursor 3} {9808065 ns} 0} {{Cursor 4} {535 ns} 0}
+WaveRestoreCursors {{Cursor 2} {9808206 ns} 0} {{Cursor 3} {9807791 ns} 0} {{Cursor 4} {85 ns} 0}
 quietly wave cursor active 1
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 513
@@ -236,4 +257,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {9808255 ns} {9808913 ns}
+WaveRestoreZoom {9807926 ns} {9808486 ns}

wally-pipelined/src/dmem/dmem.sv

@@ -63,6 +63,14 @@ module dmem (
   // *** needs to be sent to trap unit
   logic             DTLBPageFaultM;
 
+  logic [1:0] CurrState, NextState;
+
+  localparam STATE_READY = 0;
+  localparam STATE_FETCH = 1;
+  localparam STATE_STALLED = 2;
+
+  
+
   tlb #(3) dtlb(.TLBAccess(MemAccessM), .VirtualAddress(MemAdrM),
                 .PageTableEntryWrite(PageTableEntryM), .PageTypeWrite(PageTypeM),
                 .TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM),
@@ -81,8 +89,8 @@ module dmem (
 
   // Squash unaligned data accesses and failed store conditionals
   // *** this is also the place to squash if the cache is hit
-  assign MemReadM = MemRWM[1] & ~DataMisalignedM;
+  assign MemReadM = MemRWM[1] & ~DataMisalignedM & CurrState != STATE_STALLED;
-  assign MemWriteM = MemRWM[0] & ~DataMisalignedM && ~SquashSCM;
+  assign MemWriteM = MemRWM[0] & ~DataMisalignedM && ~SquashSCM & CurrState != STATE_STALLED;
   assign MemAccessM = |MemRWM;
 
   // Determine if address is valid
@@ -119,5 +127,30 @@ module dmem (
   // Data stall
   //assign DataStall = 0;
 
+  // Ross Thompson April 22, 2021
+  // for now we need to handle the issue where the data memory interface repeately
+  // requests data from memory rather than issuing a single request.
+
+
+  flopr #(2) stateReg(.clk(clk),
+		      .reset(reset),
+		      .d(NextState),
+		      .q(CurrState));
+
+  always_comb begin
+    case (CurrState)
+      STATE_READY: if (MemAccessM & ~DataMisalignedM) NextState = STATE_FETCH;
+                   else            NextState = STATE_READY;
+      STATE_FETCH: if (MemAckW & ~StallW)     NextState = STATE_READY;
+                   else if (MemAckW & StallW) NextState = STATE_STALLED;
+		   else                       NextState = STATE_FETCH;
+      STATE_STALLED: if (~StallW)             NextState = STATE_READY;
+                     else                     NextState = STATE_STALLED;
+      default: NextState = STATE_READY;
+    endcase // case (CurrState)
+  end
+  
+  
+
 endmodule
 

wally-pipelined/src/ebu/ahblite.sv

@@ -75,7 +75,8 @@ module ahblite (
   output logic [3:0]       HSIZED,
   output logic             HWRITED,
   // Stalls
-  output logic             /*InstrUpdate, */DataStall
+  output logic             /*InstrUpdate, */DataStall,
+		output logic MemAckW
   // *** add a chip-level ready signal as part of handshake
 );
 
@@ -175,6 +176,7 @@ module ahblite (
 
   assign InstrRData = HRDATA;
   assign InstrAckF = (BusState == INSTRREAD) && (NextBusState != INSTRREAD) || (BusState == INSTRREADC) && (NextBusState != INSTRREADC);
+  assign MemAckW = (BusState == MEMREAD) && (NextBusState != MEMREAD) || (BusState == MEMWRITE) && (NextBusState != MEMWRITE);
   assign MMUReadPTE = HRDATA;
   assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021
   assign CaptureDataM = ((BusState == MEMREAD) && (NextBusState != MEMREAD)) ||