From 04ac350a290cb3c35d630f734b4ac1eb2a09af0d Mon Sep 17 00:00:00 2001 From: cturek Date: Fri, 2 Dec 2022 20:31:08 +0000 Subject: [PATCH] Added flops to preproc --- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 9 ++- .../src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 81 ++++++++++--------- pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 20 ++--- 3 files changed, 57 insertions(+), 53 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 6ec0cb746..63ffab713 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -66,12 +66,13 @@ module fdivsqrt( logic WZero; logic SpecialCaseM; logic [`DIVBLEN:0] n, m; - logic OTFCSwap, ALTB, BZero, As; + logic OTFCSwap, ALTBM, BZero, As; + logic DivStartE; fdivsqrtpreproc fdivsqrtpreproc( .clk, .IFDivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, - .n, .m, .OTFCSwap, .ALTB, .BZero, .As, + .n, .m, .OTFCSwap, .ALTBM, .BZero, .As, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E); fdivsqrtfsm fdivsqrtfsm( .clk, .reset, .FmtE, .XsE, .SqrtE, @@ -85,7 +86,7 @@ module fdivsqrt( .FDivBusyE); fdivsqrtpostproc fdivsqrtpostproc( .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, - .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]), .ForwardedSrcAE, - .MDUE, .n, .ALTB, .m, .BZero, .As, + .SqrtM, .SpecialCaseM, .RemOpM(Funct3M[1]), .ForwardedSrcAE, + .n, .ALTBM, .m, .BZero, .As, .QmM, .WZero, .DivSM); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 9eec65dae..f009cfd8b 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -39,7 +39,7 @@ module fdivsqrtpostproc( input logic SqrtM, input logic SpecialCaseM, input logic [`XLEN-1:0] ForwardedSrcAE, - input logic RemOp, MDUE, ALTB, BZero, As, + input logic RemOpM, ALTBM, BZero, As, input logic [`DIVBLEN:0] n, m, output logic [`DIVb:0] QmM, output logic WZero, @@ -48,12 +48,12 @@ module fdivsqrtpostproc( logic [`DIVb+3:0] W, Sum, RemD; logic [`DIVb:0] PreQmM; - logic NegSticky, PostInc; + logic NegStickyM, PostIncM; logic weq0; - logic [`DIVBLEN:0] NormShift; - logic [`DIVb:0] IntQuot, NormQuot; - logic [`DIVb+3:0] IntRem, NormRem; - logic [`DIVb+3:0] PreResult, Result; + logic [`DIVBLEN:0] NormShiftM; + logic [`DIVb:0] IntQuotM, NormQuotM; + logic [`DIVb+3:0] IntRemM, NormRemM; + logic [`DIVb+3:0] PreResultM, ResultM; // check for early termination on an exact result. If the result is not exact, the sticky should be set aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0); @@ -77,66 +77,67 @@ module fdivsqrtpostproc( // Determine if sticky bit is negative assign Sum = WC + WS; assign W = $signed(Sum) >>> `LOGR; - assign NegSticky = W[`DIVb+3]; + assign NegStickyM = W[`DIVb+3]; assign RemD = {4'b0000, D, {(`DIVb-`DIVN+1){1'b0}}}; + // Integer division: sign handling for div and rem always_comb if (~As) - if (NegSticky) begin - NormQuot = FirstUM; - NormRem = W + RemD; - PostInc = 0; + if (NegStickyM) begin + NormQuotM = FirstUM; + NormRemM = W + RemD; + PostIncM = 0; end else begin - NormQuot = FirstU; - NormRem = W; - PostInc = 0; + NormQuotM = FirstU; + NormRemM = W; + PostIncM = 0; end else - if (NegSticky | weq0) begin - NormQuot = FirstU; - NormRem = W; - PostInc = 0; + if (NegStickyM | weq0) begin + NormQuotM = FirstU; + NormRemM = W; + PostIncM = 0; end else begin - NormQuot = FirstU; - NormRem = W - RemD; - PostInc = 1; + NormQuotM = FirstU; + NormRemM = W - RemD; + PostIncM = 1; end + // Integer division: Special cases always_comb - if(ALTB) begin - IntQuot = '0; - IntRem = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE}; + if(ALTBM) begin + IntQuotM = '0; + IntRemM = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE}; end else if (BZero) begin - IntQuot = '1; - IntRem = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE}; + IntQuotM = '1; + IntRemM = {{(`DIVb-`XLEN+4){1'b0}}, ForwardedSrcAE}; end else if (WZero) begin if (weq0) begin - IntQuot = FirstU; - IntRem = '0; + IntQuotM = FirstU; + IntRemM = '0; end else begin - IntQuot = FirstUM; - IntRem = '0; + IntQuotM = FirstUM; + IntRemM = '0; end end else begin - IntQuot = NormQuot; - IntRem = NormRem; + IntQuotM = NormQuotM; + IntRemM = NormRemM; end always_comb - if (RemOp) begin - NormShift = (m + (`DIVBLEN)'(`DIVa)); - PreResult = IntRem; + if (RemOpM) begin + NormShiftM = (m + (`DIVBLEN)'(`DIVa)); + PreResultM = IntRemM; end else begin - NormShift = ((`DIVBLEN)'(`DIVb) - (n << `LOGR)); - PreResult = {3'b000, IntQuot}; + NormShiftM = ((`DIVBLEN)'(`DIVb) - (n << `LOGR)); + PreResultM = {3'b000, IntQuotM}; end // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted - // *** Result is unused right now - assign Result = ($signed(PreResult) >>> NormShift) + {{(`DIVb+3){1'b0}}, (PostInc & ~RemOp)}; + assign ResultM = ($signed(PreResultM) >>> NormShiftM) + {{(`DIVb+3){1'b0}}, (PostIncM & ~RemOpM)}; - assign PreQmM = NegSticky ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit + assign PreQmM = NegStickyM ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit assign QmM = SqrtM ? (PreQmM << 1) : PreQmM; endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 483ce3f92..b06780996 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -42,7 +42,7 @@ module fdivsqrtpreproc ( input logic [2:0] Funct3E, Funct3M, input logic MDUE, W64E, output logic [`DIVBLEN:0] n, m, - output logic OTFCSwap, ALTB, BZero, As, + output logic OTFCSwap, ALTBM, BZero, As, output logic [`NE+1:0] QeM, output logic [`DIVb+3:0] X, output logic [`DIVN-2:0] Dpreproc @@ -56,7 +56,7 @@ module fdivsqrtpreproc ( // Intdiv signals logic [`DIVb-1:0] ZeroBufX, ZeroBufY; logic [`XLEN-1:0] PosA, PosB; - logic Bs, OTFCSwapTemp; + logic Bs, OTFCSwapTemp, ALTBE; logic [`XLEN-1:0] A64, B64; logic [`DIVBLEN:0] Calcn, Calcm; logic [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX; @@ -87,8 +87,8 @@ module fdivsqrtpreproc ( assign PreprocY = Ym[`NF-1:0]<> RightShiftX : PreShiftX; + assign X = MDUE ? DivX >> RightShiftX : PreShiftX; assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}}; // radix 2 radix 4 @@ -115,10 +115,12 @@ module fdivsqrtpreproc ( // DIVRESLEN = DIVLEN or DIVLEN+2 // r = 1 or 2 // DIVRESLEN/(r*`DIVCOPIES) - flopen #(`NE+2) expflop(clk, IFDivStartE, Qe, QeM); - flopen #(1) swapflop(clk, IFDivStartE, OTFCSwapTemp, OTFCSwap); - flopen #(`DIVBLEN+1) nflop(clk, IFDivStartE, Calcn, n); - flopen #(`DIVBLEN+1) mflop(clk, IFDivStartE, Calcm, m); + + flopen #(`NE+2) expreg(clk, IFDivStartE, Qe, QeM); + flopen #(1) swapreg(clk, IFDivStartE, OTFCSwapTemp, OTFCSwap); + flopen #(1) altbreg(clk, IFDivStartE, ALTBE, ALTBM); + flopen #(`DIVBLEN+1) nreg(clk, IFDivStartE, Calcn, n); + flopen #(`DIVBLEN+1) mreg(clk, IFDivStartE, Calcm, m); expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero, .L, .m(Calcm), .Qe); endmodule