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Update atomic.sv

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Program clean up
This commit is contained in:
Harshini Srinath 2023-06-12 13:08:54 -07:00 committed by GitHub
parent ec1aa29edc
commit 048e100805
1 changed files with 11 additions and 11 deletions
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22
src/lsu/atomic.sv
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@ -28,24 +28,24 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module atomic import cvw::*; #(parameter cvw_t P) ( module atomic import cvw::*; #(parameter cvw_t P) (
input logic clk, input logic clk,
input logic reset, input logic reset,
input logic StallW, input logic StallW,
input logic [P.XLEN-1:0] ReadDataM, // LSU ReadData XLEN because FPU does not issue atomic memory operation from FPU registers input logic [P.XLEN-1:0] ReadDataM, // LSU ReadData XLEN because FPU does not issue atomic memory operation from FPU registers
input logic [P.XLEN-1:0] IHWriteDataM, // LSU WriteData XLEN because FPU does not issue atomic memory operation from FPU registers input logic [P.XLEN-1:0] IHWriteDataM, // LSU WriteData XLEN because FPU does not issue atomic memory operation from FPU registers
input logic [P.PA_BITS-1:0] PAdrM, // Physical memory address input logic [P.PA_BITS-1:0] PAdrM, // Physical memory address
input logic [6:0] LSUFunct7M, // AMO alu operation gated by HPTW input logic [6:0] LSUFunct7M, // AMO alu operation gated by HPTW
input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size
input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation
input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal
input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation
output logic [P.XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data output logic [P.XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data
output logic SquashSCW, // Store conditional failed disable write to GPR output logic SquashSCW, // Store conditional failed disable write to GPR
output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC
); );
logic [P.XLEN-1:0] AMOResultM; logic [P.XLEN-1:0] AMOResultM;
logic MemReadM; logic MemReadM;
amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM); amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM);