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https://github.com/openhwgroup/cvw
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merged lza back into main
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commit
0482bf4fc0
@ -85,8 +85,7 @@ module fma(
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fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm, .Se, .Ss);
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fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm, .Se, .Ss);
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fmalza #(3*`NF+6) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt);
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fmalza lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt);
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endmodule
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endmodule
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@ -29,16 +29,14 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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module fmalza( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
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module fmalza #(WIDTH) ( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
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input logic [3*`NF+5:0] A, // addend
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input logic [WIDTH-1:0] A, // addend
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input logic [2*`NF+3:0] Pm, // product
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input logic [2*`NF+3:0] Pm, // product
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input logic Cin, // carry in
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input logic Cin, // carry in
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input logic sub,
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input logic sub,
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output logic [$clog2(3*`NF+7)-1:0] SCnt // normalization shift count for the positive result
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output logic [$clog2(WIDTH+1)-1:0] SCnt // normalization shift count for the positive result
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);
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);
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localparam WIDTH = 3*`NF+6;
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logic [WIDTH:0] F;
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logic [WIDTH:0] F;
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logic [WIDTH-1:0] B, P, G, K;
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logic [WIDTH-1:0] B, P, G, K;
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logic [WIDTH-1:0] Pp1, Gm1, Km1;
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logic [WIDTH-1:0] Pp1, Gm1, Km1;
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