diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 6080cacb5..146a9c946 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -64,18 +64,18 @@ module bpred import cvw::*; #(parameter cvw_t P) ( // Report branch prediction status output logic BPWrongE, // Prediction is wrong output logic BPWrongM, // Prediction is wrong - output logic BPDirPredWrongM, // Prediction direction is wrong + output logic BPDirWrongM, // Prediction direction is wrong output logic BTAWrongM, // Prediction target wrong output logic RASPredPCWrongM, // RAS prediction is wrong output logic IClassWrongM // Class prediction is wrong ); - logic [1:0] BPDirPredF; + logic [1:0] BPDirF; logic [P.XLEN-1:0] BPBTAF, RASPCF; logic BPPCWrongE; logic IClassWrongE; - logic BPDirPredWrongE; + logic BPDirWrongE; logic BPPCSrcF; logic [P.XLEN-1:0] BPPCF; @@ -104,45 +104,45 @@ module bpred import cvw::*; #(parameter cvw_t P) ( if (P.BPRED_TYPE == `BP_TWOBIT) begin:Predictor twoBitPredictor #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, + .PCNextF, .PCM, .BPDirF, .BPDirWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == `BP_GSHARE) begin:Predictor gshare #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE, + .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirF, .BPDirWrongE, .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW, .PCSrcE); end else if (P.BPRED_TYPE == `BP_GLOBAL) begin:Predictor gshare #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE, + .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirF, .BPDirWrongE, .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW, .PCSrcE); end else if (P.BPRED_TYPE == `BP_GSHARE_BASIC) begin:Predictor gsharebasic #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, + .PCNextF, .PCM, .BPDirF, .BPDirWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == `BP_GLOBAL_BASIC) begin:Predictor gsharebasic #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, + .PCNextF, .PCM, .BPDirF, .BPDirWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == `BP_LOCAL_BASIC) begin:Predictor localbpbasic #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, + .PCNextF, .PCM, .BPDirF, .BPDirWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == `BP_LOCAL_AHEAD) begin:Predictor localaheadbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE, + .PCNextF, .PCM, .BPDirD(BPDirF), .BPDirWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == `BP_LOCAL_REPAIR) begin:Predictor localrepairbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCE, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE, + .PCNextF, .PCE, .PCM, .BPDirD(BPDirF), .BPDirWrongE, .BranchD, .BranchE, .BranchM, .PCSrcE); end @@ -185,7 +185,7 @@ module bpred import cvw::*; #(parameter cvw_t P) ( flopenrc #(1) BPWrongMReg(clk, reset, FlushM, ~StallM, BPWrongE, BPWrongM); // Output the predicted PC or corrected PC on miss-predict. - assign BPPCSrcF = (BPBranchF & BPDirPredF[1]) | BPJumpF; + assign BPPCSrcF = (BPBranchF & BPDirF[1]) | BPJumpF; mux2 #(P.XLEN) pcmuxbp(BPBTAF, RASPCF, BPReturnF, BPPCF); // Selects the BP or PC+2/4. mux2 #(P.XLEN) pcmux0(PCPlus2or4F, BPPCF, BPPCSrcF, PC0NextF); @@ -217,8 +217,8 @@ module bpred import cvw::*; #(parameter cvw_t P) ( flopenrc #(P.XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); flopenrc #(P.XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); flopenrc #(2) BPPredWrongRegM(clk, reset, FlushM, ~StallM, - {BPDirPredWrongE, RASPredPCWrongE}, - {BPDirPredWrongM, RASPredPCWrongM}); + {BPDirWrongE, RASPredPCWrongE}, + {BPDirWrongM, RASPredPCWrongM}); assign BTAWrongM = BPBTAWrongM & PCSrcM; diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 9192a7cf5..149b2f353 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -37,8 +37,8 @@ module gshare import cvw::*; #(parameter cvw_t P, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] BPDirPredF, - output logic BPDirPredWrongE, + output logic [1:0] BPDirF, + output logic BPDirWrongE, // update input logic [XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, input logic BPBranchF, BranchD, BranchE, BranchM, BranchW, PCSrcE @@ -47,8 +47,8 @@ module gshare import cvw::*; #(parameter cvw_t P, logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchX; - logic [1:0] PHTBPDirPredF, BPDirPredD, BPDirPredE, FwdNewDirPredF; - logic [1:0] NewBPDirPredE, NewBPDirPredM, NewBPDirPredW; + logic [1:0] PHTBPDirF, BPDirD, BPDirE, FwdNewDirPredF; + logic [1:0] NewBPDirE, NewBPDirM, NewBPDirW; logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW; @@ -78,33 +78,33 @@ module gshare import cvw::*; #(parameter cvw_t P, assign MatchW = BranchW & ~FlushW & (IndexF == IndexW); assign MatchX = MatchD | MatchE | MatchM | MatchW; - assign FwdNewDirPredF = MatchD ? {2{BPDirPredD[1]}} : - MatchE ? {NewBPDirPredE} : - MatchM ? {NewBPDirPredM} : - NewBPDirPredW ; + assign FwdNewDirPredF = MatchD ? {2{BPDirD[1]}} : + MatchE ? {NewBPDirE} : + MatchM ? {NewBPDirM} : + NewBPDirW ; - assign BPDirPredF = MatchX ? FwdNewDirPredF : PHTBPDirPredF; + assign BPDirF = MatchX ? FwdNewDirPredF : PHTBPDirF; ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), - .rd1(PHTBPDirPredF), + .rd1(PHTBPDirF), .wa2(IndexM), - .wd2(NewBPDirPredM), + .wd2(NewBPDirM), .we2(BranchM), .bwe2(1'b1)); - flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE); + flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirF, BPDirD); + flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirD, BPDirE); - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE)); - flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM); - flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW); + satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE)); + flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirE, NewBPDirM); + flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirM, NewBPDirW); - assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE; + assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE; - assign GHRNextF = BPBranchF ? {BPDirPredF[1], GHRF[k-1:1]} : GHRF; - assign GHRF = BranchD ? {BPDirPredD[1], GHRD[k-1:1]} : GHRD; + assign GHRNextF = BPBranchF ? {BPDirF[1], GHRF[k-1:1]} : GHRF; + assign GHRF = BranchD ? {BPDirD[1], GHRD[k-1:1]} : GHRD; assign GHRD = BranchE ? {PCSrcE, GHRE[k-1:1]} : GHRE; assign GHRE = BranchM ? {PCSrcM, GHRM[k-1:1]} : GHRM; diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index 1fa6f21f6..61c3f55f0 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -36,16 +36,16 @@ module gsharebasic import cvw::*; #(parameter cvw_t P, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] BPDirPredF, - output logic BPDirPredWrongE, + output logic [1:0] BPDirF, + output logic BPDirWrongE, // update input logic [XLEN-1:0] PCNextF, PCM, input logic BranchE, BranchM, PCSrcE ); logic [k-1:0] IndexNextF, IndexM; - logic [1:0] BPDirPredD, BPDirPredE; - logic [1:0] NewBPDirPredE, NewBPDirPredM; + logic [1:0] BPDirD, BPDirE; + logic [1:0] NewBPDirE, NewBPDirM; logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; logic [k-1:0] GHRNext; @@ -62,19 +62,19 @@ module gsharebasic import cvw::*; #(parameter cvw_t P, ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), - .rd1(BPDirPredF), + .rd1(BPDirF), .wa2(IndexM), - .wd2(NewBPDirPredM), + .wd2(NewBPDirM), .we2(BranchM), .bwe2(1'b1)); - flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE); + flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirF, BPDirD); + flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirD, BPDirE); - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE)); - flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM); + satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE)); + flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirE, NewBPDirM); - assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE; + assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE; assign GHRNext = BranchM ? {PCSrcM, GHR[k-1:1]} : GHR; flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchM, GHRNext, GHR); diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index fd8acbc82..5d290e85e 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -34,18 +34,18 @@ module localaheadbp import cvw::*; #(parameter cvw_t P, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] BPDirPredD, - output logic BPDirPredWrongE, + output logic [1:0] BPDirD, + output logic BPDirWrongE, // update input logic [XLEN-1:0] PCNextF, PCM, input logic BranchE, BranchM, PCSrcE ); logic [k-1:0] IndexNextF, IndexM; - //logic [1:0] BPDirPredD, BPDirPredE; - logic [1:0] BPDirPredE; - logic [1:0] BPDirPredM; - logic [1:0] NewBPDirPredE, NewBPDirPredM, NewBPDirPredW; + //logic [1:0] BPDirD, BPDirE; + logic [1:0] BPDirE; + logic [1:0] BPDirM; + logic [1:0] NewBPDirE, NewBPDirM, NewBPDirW; logic [k-1:0] LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF; logic [k-1:0] LHRNextW; @@ -63,21 +63,21 @@ module localaheadbp import cvw::*; #(parameter cvw_t P, ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk), .ce1(~StallD), .ce2(~StallW & ~FlushW), .ra1(LHRF), - .rd1(BPDirPredD), + .rd1(BPDirD), .wa2(IndexM), - .wd2(NewBPDirPredW), + .wd2(NewBPDirW), .we2(BranchM), .bwe2(1'b1)); - //flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE); - flopenrc #(2) PredictionRegM(clk, reset, FlushM, ~StallM, BPDirPredE, BPDirPredM); + //flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirF, BPDirD); + flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirD, BPDirE); + flopenrc #(2) PredictionRegM(clk, reset, FlushM, ~StallM, BPDirE, BPDirM); - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredM), .NewState(NewBPDirPredM)); - //flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM); - flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW); + satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirM), .NewState(NewBPDirM)); + //flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirE, NewBPDirM); + flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirM, NewBPDirW); - assign BPDirPredWrongE = PCSrcE != BPDirPredM[1] & BranchE; + assign BPDirWrongE = PCSrcE != BPDirM[1] & BranchE; // This is the main difference between global and local history basic implementations. In global, // the ghr wraps back into itself directly without diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index 5c4485f3f..c2f3fdff3 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -35,16 +35,16 @@ module localbpbasic import cvw::*; #(parameter cvw_t P, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] BPDirPredF, - output logic BPDirPredWrongE, + output logic [1:0] BPDirF, + output logic BPDirWrongE, // update input logic [XLEN-1:0] PCNextF, PCM, input logic BranchE, BranchM, PCSrcE ); logic [k-1:0] IndexNextF, IndexM; - logic [1:0] BPDirPredD, BPDirPredE; - logic [1:0] NewBPDirPredE, NewBPDirPredM; + logic [1:0] BPDirD, BPDirE; + logic [1:0] NewBPDirE, NewBPDirM; logic [k-1:0] LHRF, LHRD, LHRE, LHRM, LHR; logic [k-1:0] LHRNextW; @@ -60,19 +60,19 @@ module localbpbasic import cvw::*; #(parameter cvw_t P, ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), - .rd1(BPDirPredF), + .rd1(BPDirF), .wa2(IndexM), - .wd2(NewBPDirPredM), + .wd2(NewBPDirM), .we2(BranchM), .bwe2(1'b1)); - flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE); + flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirF, BPDirD); + flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirD, BPDirE); - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE)); - flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM); + satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE)); + flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirE, NewBPDirM); - assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE; + assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE; // This is the main difference between global and local history basic implementations. In global, // the ghr wraps back into itself directly without diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index f953da0de..dac13fd44 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -34,17 +34,17 @@ module localrepairbp import cvw::*; #(parameter cvw_t P, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, - output logic [1:0] BPDirPredD, - output logic BPDirPredWrongE, + output logic [1:0] BPDirD, + output logic BPDirWrongE, // update input logic [XLEN-1:0] PCNextF, PCE, PCM, input logic BranchD, BranchE, BranchM, PCSrcE ); - //logic [1:0] BPDirPredD, BPDirPredE; - logic [1:0] BPDirPredE; - logic [1:0] BPDirPredM; - logic [1:0] NewBPDirPredE, NewBPDirPredM, NewBPDirPredW; + //logic [1:0] BPDirD, BPDirE; + logic [1:0] BPDirE; + logic [1:0] BPDirM; + logic [1:0] NewBPDirE, NewBPDirM, NewBPDirW; logic [k-1:0] LHRF, LHRD, LHRE, LHRM, LHRW, LHRNextF; logic [k-1:0] LHRNextW; @@ -62,21 +62,21 @@ module localrepairbp import cvw::*; #(parameter cvw_t P, ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) PHT(.clk(clk), .ce1(~StallD), .ce2(~StallW & ~FlushW), .ra1(LHRF), - .rd1(BPDirPredD), + .rd1(BPDirD), .wa2(LHRW), - .wd2(NewBPDirPredW), + .wd2(NewBPDirW), .we2(BranchM), .bwe2(1'b1)); - //flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE); - flopenrc #(2) PredictionRegM(clk, reset, FlushM, ~StallM, BPDirPredE, BPDirPredM); + //flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirF, BPDirD); + flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirD, BPDirE); + flopenrc #(2) PredictionRegM(clk, reset, FlushM, ~StallM, BPDirE, BPDirM); - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredM), .NewState(NewBPDirPredM)); - //flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM); - flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW); + satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirM), .NewState(NewBPDirM)); + //flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirE, NewBPDirM); + flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirM, NewBPDirW); - assign BPDirPredWrongE = PCSrcE != BPDirPredM[1] & BranchE; + assign BPDirWrongE = PCSrcE != BPDirM[1] & BranchE; // This is the main difference between global and local history basic implementations. In global, // the ghr wraps back into itself directly without @@ -100,7 +100,7 @@ module localrepairbp import cvw::*; #(parameter cvw_t P, .bwe2('1)); assign IndexLHRD = {PCE[m+1] ^ PCE[1], PCE[m:2]}; - assign LHRNextE = BranchD ? {BPDirPredD[1], LHRE[k-1:1]} : LHRE; + assign LHRNextE = BranchD ? {BPDirD[1], LHRE[k-1:1]} : LHRE; // *** replace with a small CAM ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**m), .WIDTH(k)) SHB(.clk(clk), .ce1(~StallF), .ce2(~StallE & ~FlushE), diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index 5c054175f..b65fdde7e 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -34,8 +34,8 @@ module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN, input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, input logic [XLEN-1:0] PCNextF, PCM, - output logic [1:0] BPDirPredF, - output logic BPDirPredWrongE, + output logic [1:0] BPDirF, + output logic BPDirWrongE, input logic BranchE, BranchM, input logic PCSrcE ); @@ -43,8 +43,8 @@ module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN, logic [k-1:0] IndexNextF, IndexM; logic [1:0] PredictionMemory; logic DoForwarding, DoForwardingF; - logic [1:0] BPDirPredD, BPDirPredE; - logic [1:0] NewBPDirPredE, NewBPDirPredM; + logic [1:0] BPDirD, BPDirE; + logic [1:0] NewBPDirE, NewBPDirM; // hashing function for indexing the PC // We have k bits to index, but XLEN bits as the input. @@ -57,19 +57,19 @@ module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN, ram2p1r1wbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(2**k), .WIDTH(2)) BHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), - .rd1(BPDirPredF), + .rd1(BPDirF), .wa2(IndexM), - .wd2(NewBPDirPredM), + .wd2(NewBPDirM), .we2(BranchM), .bwe2(1'b1)); - flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD); - flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE); + flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirF, BPDirD); + flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirD, BPDirE); - assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE; + assign BPDirWrongE = PCSrcE != BPDirE[1] & BranchE; - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE)); - flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM); + satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirE), .NewState(NewBPDirE)); + flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirE, NewBPDirM); endmodule diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 25ac436af..6a223c099 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -66,7 +66,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] PCM, // Memory stage instruction address // branch predictor output logic [3:0] IClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br - output logic BPDirPredWrongM, // Prediction direction is wrong + output logic BPDirWrongM, // Prediction direction is wrong output logic BTAWrongM, // Prediction target wrong output logic RASPredPCWrongM, // RAS prediction is wrong output logic IClassWrongM, // Class prediction is wrong @@ -343,7 +343,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .BranchD, .BranchE, .JumpD, .JumpE, .InstrD, .PCNextF, .PCPlus2or4F, .PC1NextF, .PCE, .PCM, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCF, .NextValidPCE, .PCD, .PCLinkE, .IClassM, .BPWrongE, .PostSpillInstrRawF, .BPWrongM, - .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM); + .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM); end else begin : bpred mux2 #(P.XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PC1NextF)); @@ -359,7 +359,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .BPReturnWrongD()); flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, BPWrongM); assign RASPredPCWrongM = 1'b0; - assign BPDirPredWrongM = BPWrongM; + assign BPDirWrongM = BPWrongM; assign BTAWrongM = BPWrongM; assign IClassM = {CallM, ReturnM, JumpM, BranchM}; assign NextValidPCE = PCE; diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index fac432251..af4dd0dd0 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -57,7 +57,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( input logic LoadStallD, StoreStallD, input logic ICacheStallF, input logic DCacheStallM, - input logic BPDirPredWrongM, + input logic BPDirWrongM, input logic BTAWrongM, input logic RASPredPCWrongM, input logic IClassWrongM, @@ -276,7 +276,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( if (P.ZICNTR_SUPPORTED) begin:counters csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM, .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM, - .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM, + .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM, .IClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM, .InterruptM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE, .CSRAdrM, .PrivilegeModeW, .CSRWriteValM, diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index f0704d0cf..e28d6c1a9 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -35,7 +35,7 @@ module csrc import cvw::*; #(parameter cvw_t P) ( input logic FlushM, input logic InstrValidNotFlushedM, LoadStallD, StoreStallD, input logic CSRMWriteM, CSRWriteM, - input logic BPDirPredWrongM, + input logic BPDirWrongM, input logic BTAWrongM, input logic RASPredPCWrongM, input logic IClassWrongM, @@ -99,7 +99,7 @@ module csrc import cvw::*; #(parameter cvw_t P) ( assign CounterEvent[4] = IClassM[1] & ~IClassM[2] & InstrValidNotFlushedM; // jump and not return instructions assign CounterEvent[5] = IClassM[2] & InstrValidNotFlushedM; // return instructions assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong - assign CounterEvent[7] = BPDirPredWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction + assign CounterEvent[7] = BPDirWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction assign CounterEvent[8] = BTAWrongM & InstrValidNotFlushedM; // branch predictor wrong target assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index c0dffcaa6..4d46b7aed 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -49,7 +49,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( input logic StoreStallD, // store instruction is stalling input logic ICacheStallF, // I cache stalled input logic DCacheStallM, // D cache stalled - input logic BPDirPredWrongM, // branch predictor guessed wrong direction + input logic BPDirWrongM, // branch predictor guessed wrong direction input logic BTAWrongM, // branch predictor guessed wrong target input logic RASPredPCWrongM, // return adddress stack guessed wrong target input logic IClassWrongM, // branch predictor guessed wrong instruction class @@ -137,7 +137,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD, - .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM, + .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM, .sfencevmaM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE, .IClassWrongM, .IClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW, diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 6ef3e2a54..c0bae7af0 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -146,7 +146,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic LSUHREADY; logic BPWrongE, BPWrongM; - logic BPDirPredWrongM; + logic BPDirWrongM; logic BTAWrongM; logic RASPredPCWrongM; logic IClassWrongM; @@ -181,7 +181,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPWrongE, .BPWrongM, // Mem .CommittedF, .EPCM, .TrapVectorM, .RetM, .TrapM, .InvalidateICacheM, .CSRWriteFenceM, - .InstrD, .InstrM, .InstrOrigM, .PCM, .IClassM, .BPDirPredWrongM, + .InstrD, .InstrM, .InstrOrigM, .PCM, .IClassM, .BPDirWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, // Faults out .IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM, @@ -291,7 +291,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF, .InstrValidM, .CommittedM, .CommittedF, .FRegWriteM, .LoadStallD, .StoreStallD, - .BPDirPredWrongM, .BTAWrongM, .BPWrongM, + .BPDirWrongM, .BTAWrongM, .BPWrongM, .RASPredPCWrongM, .IClassWrongM, .DivBusyE, .FDivBusyE, .IClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,