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https://github.com/openhwgroup/cvw
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Preparing to merge dirty and tag srams.
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pipelined/src/cache/cacheway.sv
vendored
29
pipelined/src/cache/cacheway.sv
vendored
@ -86,21 +86,28 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Tag Array
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// Tag Array
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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//logic [DIRTY_BITS+TAGLEN/8-1:0] TagByteEn;
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//logic [DIRTY_BITS+TAGLEN-1:0] TagDin, TagDout;
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//assign TagByteEn = {(SetDirtyWay | ClearDirtyWay) & ~FlushStage, {{TAGLEN/8}{SetValidEN}}};
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//assign TagDin = {SetDirtyWay, PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN] };
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//if(DIRTY_BITS) assign Dirty = TagDout[TAGLEN];
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//else assign Dirty = '0;
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//assign ReadTag = TagDout[TAGLEN-1:0];
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/* -----\/----- EXCLUDED -----\/-----
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/* -----\/----- EXCLUDED -----\/-----
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN+DIRTY_BITS)) CacheTagMem(.clk, .ce,
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localparam BYTEENLEN = DIRTY_BITS+((TAGLEN-1)/8);
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logic [BYTEENLEN:0] TagByteEn;
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logic [DIRTY_BITS+TAGLEN-1:0] TagDin, TagDout;
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if(DIRTY_BITS) begin
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assign TagByteEn = {(SetDirtyWay | ClearDirtyWay) & ~FlushStage, {{BYTEENLEN}{SetValidEN}}};
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assign TagDin = {SetDirtyWay, PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN] };
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assign Dirty = TagDout[TAGLEN];
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end else begin
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assign TagByteEn = {{BYTEENLEN}{SetValidEN}};
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assign TagDin = PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN];
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assign Dirty = '0;
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end
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assign ReadTag = TagDout[TAGLEN-1:0];
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(DIRTY_BITS+TAGLEN)) CacheTagMem(.clk, .ce,
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.addr(CAdr), .dout(TagDout), .bwe(TagByteEn),
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.addr(CAdr), .dout(TagDout), .bwe(TagByteEn),
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.din(TagDin), .we(1'b1));
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.din(TagDin), .we(1'b1));
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-----/\----- EXCLUDED -----/\----- */
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-----/\----- EXCLUDED -----/\----- */
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce,
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sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce,
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.addr(CAdr), .dout(ReadTag), .bwe({{(TAGLEN+7)/8}{SetValidEN}}),
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.addr(CAdr), .dout(ReadTag), .bwe({{(TAGLEN+7)/8}{SetValidEN}}),
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.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(1'b1));
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.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(1'b1));
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@ -513,10 +513,11 @@ module DCacheFlushFSM
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.loglinebytelen(loglinebytelen), .sramlen(sramlen))
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.loglinebytelen(loglinebytelen), .sramlen(sramlen))
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copyShadow(.clk,
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copyShadow(.clk,
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.start,
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.start,
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.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index]),
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.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
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.valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
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.valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
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//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
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//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
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.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
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.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
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//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]),
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.data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.RAM[index]),
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.data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.RAM[index]),
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.index(index),
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.index(index),
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.cacheWord(cacheWord),
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.cacheWord(cacheWord),
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