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Preparing to merge dirty and tag srams.

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This commit is contained in:
Ross Thompson 2022-11-30 10:40:48 -06:00
parent de538d1c2f
commit 0454eb95ad
2 changed files with 20 additions and 12 deletions
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29
pipelined/src/cache/cacheway.sv vendored
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@ -86,21 +86,28 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
// Tag Array // Tag Array
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
//logic [DIRTY_BITS+TAGLEN/8-1:0] TagByteEn;
//logic [DIRTY_BITS+TAGLEN-1:0] TagDin, TagDout;
//assign TagByteEn = {(SetDirtyWay | ClearDirtyWay) & ~FlushStage, {{TAGLEN/8}{SetValidEN}}};
//assign TagDin = {SetDirtyWay, PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN] };
//if(DIRTY_BITS) assign Dirty = TagDout[TAGLEN];
//else assign Dirty = '0;
//assign ReadTag = TagDout[TAGLEN-1:0];
/* -----\/----- EXCLUDED -----\/----- /* -----\/----- EXCLUDED -----\/-----
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN+DIRTY_BITS)) CacheTagMem(.clk, .ce, localparam BYTEENLEN = DIRTY_BITS+((TAGLEN-1)/8);
logic [BYTEENLEN:0] TagByteEn;
logic [DIRTY_BITS+TAGLEN-1:0] TagDin, TagDout;
if(DIRTY_BITS) begin
assign TagByteEn = {(SetDirtyWay | ClearDirtyWay) & ~FlushStage, {{BYTEENLEN}{SetValidEN}}};
assign TagDin = {SetDirtyWay, PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN] };
assign Dirty = TagDout[TAGLEN];
end else begin
assign TagByteEn = {{BYTEENLEN}{SetValidEN}};
assign TagDin = PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN];
assign Dirty = '0;
end
assign ReadTag = TagDout[TAGLEN-1:0];
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(DIRTY_BITS+TAGLEN)) CacheTagMem(.clk, .ce,
.addr(CAdr), .dout(TagDout), .bwe(TagByteEn), .addr(CAdr), .dout(TagDout), .bwe(TagByteEn),
.din(TagDin), .we(1'b1)); .din(TagDin), .we(1'b1));
-----/\----- EXCLUDED -----/\----- */ -----/\----- EXCLUDED -----/\----- */
sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce, sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce,
.addr(CAdr), .dout(ReadTag), .bwe({{(TAGLEN+7)/8}{SetValidEN}}), .addr(CAdr), .dout(ReadTag), .bwe({{(TAGLEN+7)/8}{SetValidEN}}),
.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(1'b1)); .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(1'b1));

3
pipelined/testbench/testbench.sv
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@ -513,10 +513,11 @@ module DCacheFlushFSM
.loglinebytelen(loglinebytelen), .sramlen(sramlen)) .loglinebytelen(loglinebytelen), .sramlen(sramlen))
copyShadow(.clk, copyShadow(.clk,
.start, .start,
.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index]), .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
.valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]), .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]), //.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]), .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]),
.data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.RAM[index]), .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.RAM[index]),
.index(index), .index(index),
.cacheWord(cacheWord), .cacheWord(cacheWord),